| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-09-10 | style: fix sorting of includes and whitespace in some files | Nathan Binkert | |
| 2010-08-31 | ARM: Get rid of the checkFpEnableFault function in ARM. | Gabe Black | |
| 2010-08-31 | Alpha: Alpha's mt.hh was including mips header files. | Gabe Black | |
| 2010-08-27 | X86: Change the copyright holder to AMD. | Gabe Black | |
| I accidentally left myself as a placeholder copyright holder on this file when I checked it in. Copyright should be assigned to AMD. | |||
| 2010-08-25 | ARM: Support unaligned memory access. | Min Kyu Jeong | |
| Without this flag set, page-crossing requests were not split into two mem request. Depending on the alignment bit in the SCTLR, misaligned access could raise a fault. However it seems unnecessary to implement that. | |||
| 2010-08-25 | ARM: Seperate the queues of L1 and L2 walker states. | Gene WU | |
| 2010-08-25 | ARM: Adding a bogus fault that does nothing. | Min Kyu Jeong | |
| This fault can used to flush the pipe, not including the faulting instruction. The particular case I needed this was for a self-modifying code. It needed to drain the store queue and force the following instruction to refetch from icache. DCCMVAC cp15 mcr instruction is modified to raise this fault. | |||
| 2010-08-25 | ARM: Remove ALPHA KSeg functions. | William Wang | |
| These were erronously copied years ago into the ARM directory. | |||
| 2010-08-25 | ARM: Limited implementation of dprintk. | Ali Saidi | |
| Does not work with vfp arguments or arguments passed on the stack. | |||
| 2010-08-25 | ARM: Fixed register flattening logic (FP_Base_DepTag was set too low) | Min Kyu Jeong | |
| When decoding a srs instruction, invalid mode encoding returns invalid instruction. This can happen when garbage instructions are fetched from mispredicted path | |||
| 2010-08-25 | ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing | Ali Saidi | |
| 2010-08-25 | ARM: Use fewer micro-ops for register update loads if possible. | Gene WU | |
| Allow some loads that update the base register to use just two micro-ops. three micro-ops are only used if the destination register matches the offset register or the PC is the destination regsiter. If the PC is updated it needs to be the last micro-op otherwise O3 will mispredict. | |||
| 2010-08-25 | ARM: Set the high bits in the part number so it's considered new by some code. | Ali Saidi | |
| 2010-08-25 | ARM: Fix VFP enabled checks for mem instructions | Ali Saidi | |
| 2010-08-25 | ARM: Seperate out the renamable bits in the FPSCR. | Gabe Black | |
| 2010-08-25 | ARM: Eliminate some unused enums. | Gabe Black | |
| 2010-08-25 | ARM: Fix type comparison warnings in Neon. | Gabe Black | |
| 2010-08-25 | ARM: Implement CPACR register and return Undefined Instruction when FP ↵ | Gabe Black | |
| access is disabled. | |||
| 2010-08-25 | ARM: Implement all ARM SIMD instructions. | Gabe Black | |
| 2010-08-25 | ARM: Expand the mode checking utility functions. | Gabe Black | |
| inUserMode now can take either a threadcontext or a CPSR value directly. If given a thread context it just extracts the CPSR and calls the other version. An inPrivelegedMode function was also implemented which just returns the opposite of inUserMode. | |||
| 2010-08-23 | X86: Create a directory for files that define register indexes. | Gabe Black | |
| This is to help tidy up arch/x86. These files should not be used external to the ISA. --HG-- rename : src/arch/x86/apicregs.hh => src/arch/x86/regs/apic.hh rename : src/arch/x86/floatregs.hh => src/arch/x86/regs/float.hh rename : src/arch/x86/intregs.hh => src/arch/x86/regs/int.hh rename : src/arch/x86/miscregs.hh => src/arch/x86/regs/misc.hh rename : src/arch/x86/segmentregs.hh => src/arch/x86/regs/segment.hh | |||
| 2010-08-23 | Power: Get rid of unused checkFpEnableFault. | Gabe Black | |
| This function was brought in from another ISA and doesn't actually do anything or get used. | |||
| 2010-08-23 | ISA: Get rid of old, unused utility functions cluttering up the ISAs. | Gabe Black | |
| 2010-08-23 | X86: Get rid of the flagless microop constructor. | Gabe Black | |
| This will reduce clutter in the source and hopefully speed up compilation. | |||
| 2010-08-23 | X86: Make the TLB fault instead of panic when something is unmapped in SE mode. | Gabe Black | |
| The fault object, if invoked, would then panic. This is a bit less direct, but it means speculative execution won't panic the simulator. | |||
| 2010-08-23 | X86: Make the x86 ExtMachInst serializable with (UN)SERIALIZE_SCALAR. | Gabe Black | |
| --HG-- rename : src/arch/x86/types.hh => src/arch/x86/types.cc | |||
| 2010-08-23 | X86: Define a noop ExtMachInst. | Gabe Black | |
| 2010-08-23 | X86: Mark serializing macroops and regular instructions as such. | Gabe Black | |
| 2010-08-23 | X86: Add a .serializing directive that makes a macroop serializing. | Gabe Black | |
| This directive really just tells the macroop to set IsSerializing and IsSerializeAfter on its final microop. | |||
| 2010-08-23 | X86: Consolidate extra microop flags into one parameter. | Gabe Black | |
| This single parameter replaces the collection of bools that set up various flavors of microops. A flag parameter also allows other flags to be set like the serialize before/after flags, etc., without having to change the constructor. | |||
| 2010-08-23 | ARM: Improve printing of uop disassembly. | Min Kyu Jeong | |
| 2010-08-23 | ARM: Clean up flattening for SPSR adding | Min Kyu Jeong | |
| 2010-08-23 | ARM: Implement DBG instruction that doesn't do much for now. | Gene Wu | |
| 2010-08-23 | MEM: Make CLREX a first class request operation and clear locks in caches ↵ | Gene Wu | |
| when it in received | |||
| 2010-08-23 | ARM: Make sure that software prefetch instructions can't change the state of ↵ | Gene Wu | |
| the TLB | |||
| 2010-08-23 | ARM: Don't write tracedata on writes, it might have been freed already. | Gene Wu | |
| 2010-08-23 | ARM: Implement CLREX init/complete acc methods | Gene Wu | |
| 2010-08-23 | ARM: Fix Uncachable TLB requests and decoding of xn bit | Gene Wu | |
| 2010-08-23 | ARM: For non-cachable accesses set the UNCACHABLE flag | Gene Wu | |
| 2010-08-23 | ARM: Implement DSB, DMB, ISB | Gene Wu | |
| 2010-08-23 | ARM: Get SCTLR TE bit from reset SCTLR | Gene Wu | |
| 2010-08-23 | ARM: Implement CLREX | Gene Wu | |
| 2010-08-23 | ARM: BX instruction can be contitional if last instruction in a IT block | Gene Wu | |
| Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond. | |||
| 2010-08-23 | ARM: mark msr/mrs instructions as SerializeBefore/After | Min Kyu Jeong | |
| Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR | |||
| 2010-08-23 | ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate. | Min Kyu Jeong | |
| THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false. | |||
| 2010-08-23 | ARM: adding genMachineCheckFault() stub for ARM that doesn't panic | Min Kyu Jeong | |
| 2010-08-23 | ARM: DFSR status value for sync external data abort is expected to be 0x8 in ↵ | Gene Wu | |
| ARMv7 | |||
| 2010-08-23 | ARM: Temporary local variables can't conflict with isa parser operands. | Gene Wu | |
| PC is an operand, so we can't have a temp called PC | |||
| 2010-08-23 | ARM: Exclusive accesses must be double word aligned | Ali Saidi | |
| 2010-08-23 | ARM: Add some registers for big loads/stores to support neon. | Ali Saidi | |
 |
index : gem5 | |
| gem5 |
| summaryrefslogtreecommitdiff |