summaryrefslogtreecommitdiff
path: root/src/arch
AgeCommit message (Expand)Author
2019-05-30arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.Gabe Black
2019-05-30arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.Gabe Black
2019-05-29sim-se: add a release parameter to Process.pyCiro Santilli
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
2019-05-29arm, mem: Move the SecurePortProxy subclass into it's own file.Gabe Black
2019-05-24arch-arm: Fix fallthrough when trapping at EL2Giacomo Travaglini
2019-05-23arch-arm: Trap virtual accesses to GICv3 SGI registersGiacomo Travaglini
2019-05-23arch-arm: Expose haveGicv3CPUInterface to the ISA interfaceGiacomo Travaglini
2019-05-23arch-arm: Change mcrMrc15TrapToHyp signatureGiacomo Travaglini
2019-05-22sim-se: remove comment for code that movedBrandon Potter
2019-05-21sim-se: change syscall function signatureBrandon Potter
2019-05-20x86: Add an object file loader for linux.Gabe Black
2019-05-20sparc: Add an object file loader for linux and solaris.Gabe Black
2019-05-20riscv: Add an object file loader for linux.Gabe Black
2019-05-20power: Add an object file loader for linux.Gabe Black
2019-05-20mips: Add an object file loader for linux.Gabe Black
2019-05-18arm: Add an object file loader for linux and freebsd.Gabe Black
2019-05-18alpha: Add an object file loader for linux.Gabe Black
2019-05-18arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.Gabe Black
2019-05-17arch-arm: implement VMINNM and VMAXNM scalar versionCiro Santilli
2019-05-17arch-arm: implement VMINNM and VMAXNM SIMD versionCiro Santilli
2019-05-17arch-arm: rename operands to match spec in isa/formats/fp.isaCiro Santilli
2019-05-14arch-arm: Do not check MustBeOne flag for TLB requests from the prefetcherJavier Bueno
2019-05-11arch-arm: Add initial support for SVE contiguous loads/storesGiacomo Gabrielli
2019-05-07x86: Mark translation as delayed in case of a hw page table walkGabor Dozsa
2019-05-04arch-riscv: Implement MHARTID CSRAlec Roelke
2019-05-03sim-se: add eventfd system callBrandon Potter
2019-05-03arch-riscv,isa: Fix for compressed jump (c_j) immAvishai Tvila
2019-04-30arch: Stop using TheISA within the ISAs.Gabe Black
2019-04-30x86: Get rid of some unnecessary TheISA-es in x86.Gabe Black
2019-04-30sparc: Move translation constants from isa_traits.hh into tlb.hh.Gabe Black
2019-04-30sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.Gabe Black
2019-04-30arch: Remove the mt.hh switching header.Gabe Black
2019-04-30cpu: alpha: Delete all occurrances of the simPalCheck function.Gabe Black
2019-04-30alpha: Implement simPalCheck within the ISA description.Gabe Black
2019-04-30cpu: Remove hwrei from the generic interfaces.Gabe Black
2019-04-30arch: cpu: Track kernel stats using the base ISA agnostic type.Gabe Black
2019-04-30alpha: Implement HWREI in the ISA.Gabe Black
2019-04-30alpha: Add some control registers to the ISA operands list.Gabe Black
2019-04-29mips: Implement readRegOtherThread and setRegOtherThread directly.Gabe Black
2019-04-29arch-arm: Faults DebugFlag now printing inst opcode if availableGiacomo Travaglini
2019-04-29arch-arm: Report real instruction encoding when UndefinedGiacomo Travaglini
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
2019-04-28mem: Remove the ISA specialized versions of port proxy's read/write.Gabe Black
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-04-26arch-arm: updateMiscReg not setting isHyp in aarch64Giacomo Travaglini
2019-04-26arm: Factor some repetition out of the ProcessInfo constructor.Gabe Black
2019-04-25arm: Fix some style issues in stacktrace.cc.Gabe Black
2019-04-25x86: Refactor the ProcessInfo constructor.Gabe Black
2019-04-25x86: Fix some style issues in stacktrace.cc.Gabe Black