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AgeCommit message (Expand)Author
2019-12-10arch: Get rid of the now unused setSyscallArg.Gabe Black
2019-12-10arch: Stop using setSyscallArg to set argc and argv.Gabe Black
2019-12-10arch: Use ignoreWarnOnceFunc instead of the WarnOnce flag.Gabe Black
2019-12-10arch-arm: Disambuiguate NumFloatV7ArchRegs usageGiacomo Travaglini
2019-12-10arch-arm: Unify VLdmStm behaviour when reg out of indexGiacomo Travaglini
2019-12-10arch-arm: Fix NumVecV7ArchRegs value (64->16)Giacomo Travaglini
2019-12-10arch-arm: Reorder arch/arm/registers.hh constantsGiacomo Travaglini
2019-12-10arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegsGiacomo Travaglini
2019-12-08arch-riscv: set MaxMiscDestRegs to 2Alec Roelke
2019-12-06kvm,arm: Update the KVM ARM v8 CPU to use vector regs.Gabe Black
2019-12-05arch-x86: missing override specifierAndrea Mondelli
2019-12-05arch-x86: Adding LDDQU instructionmarjanfariborz
2019-12-04sparc: Fix the getresuidFunc prototype.Gabe Black
2019-12-04sparc: Fix the predecoder's moreBytes method.Gabe Black
2019-12-03fastmodel: Switch the diagnostic pragmas to GCC from clang.Gabe Black
2019-12-03systemc,fastmodel: Use the gem5_scons error and warning functions.Gabe Black
2019-12-03fastmodel: Suppress a spurious warning on clang for amba_pv.h.Gabe Black
2019-12-01arch-riscv: Fix disassembling of immediate for c.lui instructionIan Jiang
2019-11-28arm: Make sure not to shift off of the end of a uint32_t in KVM.Gabe Black
2019-11-26arch-arm: Make the Tarmac parsed registers case insensitiveGiacomo Travaglini
2019-11-26arch-riscv: Fix immediate decoding for integer shift immediate instructionsIan Jiang
2019-11-26arch-riscv: Fix disassembling for fence and fence.iIan Jiang
2019-11-26arch,cpu: Get rid of ISA_HAS_CC_REGS and its associated ifdefs.Gabe Black
2019-11-25arm: Stop serializing ISA values wihch are cached from the system.Gabe Black
2019-11-25arch-arm: default MIDR for Armv8 ISA processorsAdrian Herrera
2019-11-25arch-riscv: Fix disassembling for atomic instructionsIan Jiang
2019-11-25arch-riscv: Fix disassembling of operand list for compressed instructionsIan Jiang
2019-11-25arch-riscv: Fix disassembling of immediate for U-type instructionsIan Jiang
2019-11-22arch-riscv: Fix bug in serialize and unserialize of InterrutpsIanJiangICT
2019-11-20base,tests: Expanded GTests for addr_range.hhBrandon Potter
2019-11-18arch: Get rid of the (Big|Little)EndianGuest namespaces.Gabe Black
2019-11-18arch: Make and use endian specific versions of the mem helpers.Gabe Black
2019-11-18arch-arm: R/W interface to AArch32 HCR2 misc regAdrian Herrera
2019-11-18arch-arm: Fix short descriptors cacheability during table walksGiacomo Travaglini
2019-11-18arch-arm: Fix long descriptors cacheability during table walksGiacomo Travaglini
2019-11-14arch-arm: Refactor code to check if gic is GicV2Chun-Chen TK Hsu
2019-11-14config: Add fastmodel cluster in fs_bigLITTLE.pyChun-Chen TK Hsu
2019-11-13arm: Replace most htog and gtoh with htole and letoh.Gabe Black
2019-11-13arch-arm: fix routeToHyp for AArch64 in faultsAdrian Herrera
2019-11-13fastmodel: Implement reading vector registers with readVecReg.Gabe Black
2019-11-11arch-arm: Fix TarmacParser handling of 64bit LD/STGiacomo Travaglini
2019-11-11arch-arm: Provide SVE support to the TarmacTracerGiacomo Travaglini
2019-11-11arch-arm: Provide SVE support to the TarmacParserGiacomo Gabrielli
2019-11-07arm: Set the number of FloatRegs to zero.Gabe Black
2019-11-07power: Replace gtoh and htog with betoh and htobe.Gabe Black
2019-11-07x86: Replace htog and gtoh with htole and letoh.Gabe Black
2019-11-07mips: Replace gtoh and htog with letoh and htole.Gabe Black
2019-11-07sparc: Replace htog and gtoh with htobe and betoh.Gabe Black
2019-11-07fastmodel: Plumb the ITB and DTB through the IRIS thread context.Gabe Black
2019-11-06fastmodel: Implement inst count events in the IRIS thread contexts.Gabe Black
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