summaryrefslogtreecommitdiff
path: root/src/arch
AgeCommit message (Collapse)Author
2019-10-15arch-x86: Make LFENCE a serializing instructionIsaac Richter
According to the Intel SDM, no instruction following an LFENCE can begin execution until after the LFENCE has executed. (This is less strict than an actual serializing instruction, such as CPUID.) Serializing instructions (per intel SDM Volume 3A Chapter 8.3) ensure that no future instruction is fetched until after the serializing instruction is completed. By contrast, LFENCE (and other memory-ordering instructions) allows future instructions to have been fetched; it just prohibits them from being executed. Change-Id: If89fcb552192326ab69a581f57d71c95cf5d90e7 Signed-off-by: Isaac Richter <isaac.richter@rochester.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10321 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-15x86: De-x86ify the IntMasterPort.Gabe Black
The devices which host an IntMasterPort are very specific to x86 at the moment, but the ports don't have to be. This change moves responsibilities around so that the x86 specific aspects are handled in the device, and the ports themselves are ISA agnostic. Change-Id: I50141b66895be7d8f6303605505002ef424af7fd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20827 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-14x86: Simplify and consolidate the code that assembles an MSI on x86.Gabe Black
There is no interrupt response message, and so no need for a function which would construct one. The other functions which construct the request can be consolidated since the work being done by each is incremental. The template parameters can be used to support multiple types and offsets in a single function, and since that function also doesn't have to do much work, it makes sense to do everything in one shot. Change-Id: I41b202a263a697c5ada6817f3ab2a4728281b894 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20826 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-10-14fastmodel: Expose all CPU communication ports from the GIC.Gabe Black
The unconnected CPU ports/sockets still need to be connected for TLM to be happy, so this change also adds a terminator module which finds all unbound sockets, creates pair sockets for them to connect to, binds everything together, and implements the target interface with a dummy stub that will complain and crash gem5 if it ever gets called. This will allow us to use the same GIC model to connect an arbitrary number of cores, up to the architected limit of 256. Change-Id: Iaa83fe4f023217dc91a3734b31f764fc4176130e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21500 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-12x86: Stop using and delete the x86 IntDevice class.Gabe Black
Most of its functionality has been exported already. This change makes the two classes which were inheriting IntDevice create an IntMasterPort themselves. Change-Id: I73d17cd79cf8252b0e26dd2576f552bf9054adf4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20825 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-12arch,base: Separate the idea of a memory image and object file.Gabe Black
A memory image can be described by an object file, but an object file is more than a memory image. Also, it makes sense to manipulate a memory image to, for instance, change how it's loaded into memory. That takes on larger implications (relocations, the entry point, symbols, etc.) when talking about the whole object file, and also modifies aspects which may not need to change. For instance if an image needs to be loaded into memory at addresses different from what's in the object file, but other things like symbols need to stay unmodified. Change-Id: Ia360405ffb2c1c48e0cc201ac0a0764357996a54 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21466 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-10-10arch,base: Stop loading the interpreter in ElfObject.Gabe Black
The interpreter is a separate object file, and while it's convenient to hide loading it in the code which loads the main object file, it breaks the conceptual abstraction since you only asked it to load the main object file. Also, this makes every object file format reimplement the idea of loading the interpreter. Admittedly only ELF recognizes and sets up an interpreter, but other formats conceptually could too. This does move that limitted hypothetical redundancy out of the object file formats and moves it into the process objects, but I think conceptually that's where it belongs. It would also probably be pretty easy to add a method to the base Process class that would handle loading an image and also the interpreter image. This change does not (yet) separate reading symbol tables. Change-Id: I4a165eac599a9bcd30371a162379e833c4cc89b4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21465 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-10-10arch-arm: Move generateDtb to ArmSystemGiacomo Travaglini
This is aligning with the fact that dtb autogeneration is already possible with an ArmSystem. Change-Id: I72149927ee70d29458f8718a03845bb293c12145 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21602 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-10dev-arm, configs: Remove RealViewPBX platformGiacomo Travaglini
This is an old unused platform. We should support VExpress_GEM5 based platforms only. Change-Id: If9c29047b2d068992dfbbe0dc268c70b788cce5f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21601 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-10arch, base: Stop assuming object files have three segments.Gabe Black
The ObjectFile class has hardcoded assumptions that there are three segments, text, bss and data. There are some files which have one "segment" like raw files, where the entire file's contents are considered a single segment. There are also ELF files which can have an arbitrary number of segments, and those segments can hold any number of sections, including the text, data and/or bss sections. Removing this assumption frees up some object file formats from having to twist themselves to fit in that structure, possibly introducing ambiguities when some segments may fulfill multiple roles. Change-Id: I976e06a3a90ef852b17a6485e2595b006b2090d5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21463 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-10-09fastmodel: Export GICV3Comms directly.Gabe Black
This lets us avoid having to have two levels of bridging and twice as many ports on both the CPU and GIC side. The direct communication ports can be instantiated and connected using array syntax, where the bridges require instantiating each bridge individually and wiring them up one at a time with a lot of boilerplate/duplicate code. Change-Id: I815ee47bcd19994e46a5220e0c23e89c497d7aa5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21050 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-09arch-mips,arch-riscv,base: Get rid of the unused HexFile class.Gabe Black
A pointer to it was set up in the MIPS and RISCV system classes, but nothing ever set that pointer. The class was put in base/loader, but didn't have anything to do (as far as I can see) with loading anything it had a loadSegments method, but was not a subclass of ObjectFile. Change-Id: I4b711a31df20e20ffc306709227f60aa020fca15 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21464 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-09base: Rename Section to Segment, and some of its members.Gabe Black
ELF is, in my opinion, the most important object file format gem5 currently understands, and in ELF terminolgy the blob of data that needs to be loaded into memory to a particular location is called a segment. A section is a software level view of what's in a region of memory, and a single segment may contain multiple sections which happen to follow each other in memory. Change-Id: Ib810c5050723d5a96bd7550515b08ac695fb1b02 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21462 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-10-08base: Get rid of the unused global pointer in object files.Gabe Black
This was only ever read from Alpha, and nothing ever set it. It defaulted to zero, so this change just propogates that value through to the Alpha Process class. Change-Id: I569cf9d61a37322dbd88de1038a2af74c64bbe7a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21461 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-07fastmodel: Make CortexA76x1's interrupts use gem5's mechanisms.Gabe Black
This makes it easier to wire up CPUs to the interrupt controller, and makes things more modular. Change-Id: I8d3ab26e4bb588b8efb198ed145d0f58b7ee04cb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21049 Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-07kvm, arm: fix the size of MISCREG_FPSR and MISCREG_FPCRCiro Santilli
Those registers are 32-bit instead of 64 in the KVM API. The Linux kernel 5.2 linux/Documentation/virtual/kvm/api.txt contains: 0x6020 0000 0010 00d4 FPSR 32 fp_regs.fpsr 0x6020 0000 0010 00d5 FPCR 32 fp_regs.fpcr The register itself is 64-bit in the ARM manual, but the top 32 are RES0. This fixes the following error when running ARM KVM early in the simulation: panic: KVM: Failed to set register (0x60300000001000d4) value (errno: 22) Change-Id: I8fe6e12df4809992173200a42e3ce5414748bdad Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21300 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-03arch-arm: Annotate CM flag in AA64 CM InstructionsGiacomo Travaglini
DC ZVA instruction is not classified as a cache maintenance instruction, and therefore its execution cannot cause this field to be set to 1. Change-Id: I0f30db1e6fc629dc52293edfb2bac4cf99ee49cc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21306 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-03arch-arm: Set CM bit in DataAbortGiacomo Travaglini
The CM bit in a DataAbort ISS indicates whether the Data Abort came from a cache maintenance or address translation instruction. Change-Id: I8888520446550581c8dd0507a8989935db7047be Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21305 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-02arch-arm: Create helper for sending events (SEV)Giacomo Travaglini
Events can be generated by devices, so we need an interface devices can use to notify events to PEs. Change-Id: I330575e7d116388d5f9260ef4400b0feaa861f3e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21301 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-02fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU.Gabe Black
This was to support port proxies and getInstPort and getDataPort. With some recent upstream changes, getInstPort and getDataPort are only used for CPU switching which we can't support (TLM ports are bound permanently), and with the sendFunctional delegate for port proxies, we don't need to have a traditional gem5 port lying around. This gets rid of the "mem" port and all its plumbing. Change-Id: Ic68a40a26b24aa05b33da0510c9f4b7621cbf578 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21048 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-02fastmodel: Implement a custom sendFunctional for CortexA76x1.Gabe Black
Change-Id: I28094620106a8edd90e1144b4fb87ae5729ebf32 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21047 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-02x86: Switch from MessageReq and Resp to WriteReq and Resp.Gabe Black
Originally MessageReq was intended to mark a packet as a holding a message destined for a particular recipient and which would not interact with other packets. This is similar to the way a WriteReq would behave if writing to a device register which needs to be updated atomically. Also, while the memory system *could* recognize a MessageReq and know that it didn't need to interact with other packets, that was never implemented. Change-Id: Ie54301d1d8820e206d6bae96e200ae8c71d2d784 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20823 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-02fastmodel: Let the EVS set an attribute for getSendFunctional to return.Gabe Black
The iris CPU model doesn't necessarily know the best way to send functional packets (what port? what type is that port?), but only has a generic sc_module pointer to the EVS and so can't call specialized methods on it. There also isn't any common base class for EVSes to cast into in a generic way. This attribute mechanism lets the EVS set up its own sendFunctional implementation however it needs to using facilities that are built into generic sc_objects. Change-Id: I69bf364908c2a5360bd6ce7d3e49ce67c6f771b0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21046 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-01fastmodel: Add a gem5Cpu attribute to the CortexA76x1.Gabe Black
This attribute is to let the fast model EVS CPU find and talk to the gem5 CPU in case it needs a pointer to one of its ThreadContexts for instance. Also move the code that finds the clock period attribute/event to the constructor. gem5 guarantees that the EVS is constructed before its pointer is passed to the iris CPU wrapper, and so the EVS will have had a chance to install those controls if it's going to. Change-Id: I389ef0ba0f9d528140f40444baa5091a9ec338cd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21045 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-01fastmodel: Add a utility class which makes it easier to watch signals.Gabe Black
These signals come from the exported virtual subsystem and could signal interrupts, etc. The new SignalReceiver class makes it easier to watch those signals and perform some behavior when they change without having to bring along a lot of systemc baggage. Change-Id: I09651de1dd0e7340a61779aaf080c695ce299fd4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21043 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-01fastmodel: Pull out and simplify the interrupt mechanism in the GIC.Gabe Black
This change pulls out the SPI and PPI command structures and replaces them with a custom protocol which can deliver a SPI or PPI without having to bundle their parameters into a structure. Change-Id: I8f15c8b3182bd6560bf5ef0345b0bc64173def85 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21042 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-27fastmodel: Add glue code which adapts fastmodels to run in gem5.Gabe Black
Fast Models are models written by ARM which emulate different components of a computer system. They can be combined into small subsystems and then exported as systemc modules. To enable this code, you'll need to set USE_ARM_FASTMODEL variable to true. This CL does not include the fast models themselves, or a license to use them or the associated tools. To build these fast models, you'll need to set some scons variables. These variables should be set as described in the fast model distribution. * PVLIB_HOME * MAXCORE_HOME * ARMLMD_LICENSE_FILE Some minor patches to source filesdistributed with the fast model code may be necessary since their use of systemc is not necessarily 100% standards compliant. Change-Id: Id53814b95d8aa320da4d4f2159be0736fc12eb73 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20799 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-23cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>Jordi Vaquero
This change is based on modify the way we move the AtomicOpFunctor* through gem5 in order to mantain proper ownership of the object and ensuring its destruction when it is no longer used. Doing that we fix at the same time a memory leak in Request.hh where we were assigning a new AtomicOpFunctor* without destroying the previous one. This change creates a new type AtomicOpFunctor_ptr as a std::unique_ptr<AtomicOpFunctor> and move its ownership as needed. Except for its only usage when AtomicOpFunc() is called. Change-Id: Ic516f9d8217cb1ae1f0a19500e5da0336da9fd4f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20919 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-21x86: Templatize the IntMasterPort.Gabe Black
This makes the IntMasterPort usable with any class, making it possible to avoid inheriting from IntDevice. It also makes IntMasterPort inherit directly from QueuedMasterPort, skipping over MessageMasterPort. Change-Id: I9d218556c838ea567ced5f6fa4d57a3ec9d28d31 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20821 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-09-21x86: Templatize IntSlavePort.Gabe Black
This makes the device IntSlavePort calls back into based on a template parameter so that IntDevice doesn't have to be in the inheritance hierarchy to use it. It also makes IntSlavePort inherit from SimpleTimingPort directly, skipping over MessageSlavePort. Change-Id: Ic3213edc9c3ed5e506ee1e9f5e082cd47d7c7998 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20820 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-09-21x86: Turn the local APIC into a PioDevice instead of a BasicPioDevice.Gabe Black
This will let us accept several address ranges through our pio port instead of just one, and that will in turn let us accept interrupt requests and pio requests through the same port. Change-Id: I70b78c8cd0edca7fe58b3d4cd241e41d9e0f2c20 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20819 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-20arch-x86: ignore non-temporal hint for movntps/movntpd SSE instsPouya Fotouhi
Making the implementation of movntps/movntpd consistent with other non-temporal instructions. We are ignoring the hint here, and implementing those instructions as cacheable instructions. This change adds a warning to let user know about this workaround. Also, this change add the address check for second part of move. Change-Id: I811652b24cf39ca2f5c5d4c9e9e417f69190b55c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20408 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-19arch-x86: Change warn to warn_once for NT instructionsHoa Nguyen
Change-Id: I50353716f2a913b9b106b140644d95991879f662 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21039 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-19arch-arm: PSTATE.PAN changes should inval cached regs in TLBGiacomo Travaglini
Change-Id: Id94e355fec345d2e952539a7dce7fbd21ed220c6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20983 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-18arch-arm: Fix Data Abort ISS when caused by Atomic operationGiacomo Travaglini
Data Aborts caused by an atomic instruction have a special rule for their syndrome: From a ISS point of view they count as read if a read to that address would generate a fault; they count as writes otherwise (ISS.WnR bit) This patch is implementing this in the TLB. For permission faults we need to explicitly check if a read would trigger a fault (e.g. checking for the AP bits) since permissions can allow read-only accesses. For other MMU exceptions (like translation faults) we are confident the nature of the access doesn't affect the genration of a fault. This means that if the access is atomic, we treat it as a read from an ISS.WnR point of view. Change-Id: Ia524aa6ae07f81513cdc26c516b5fd9b01a931c3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20981 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-18arch-arm: ISV bit in DataAbort should check for translation stageGiacomo Travaglini
According to the ESR spec, the ISV bit is set to 1 only for stage 2 aborts. Change-Id: Id524ef36e82184f741e968ddba04ca8ccdd4ad58 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20980 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-18arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2.E2H=1Giacomo Travaglini
Change-Id: I6df0cdcbadca17f30d3de3bed887f75c739b00f0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20979 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-18arch, x86: Rework the debug faults and microops.Gabe Black
This makes the non-fatal microops advance the PC, and adds missing functions. The *_once Faults now also can be run once per *something*. They would previously be run once per Fault invoke function which is common to all M5WarnOnceFaults. The warn_once microop will now warn once per message. Change-Id: I05974b93f3b2700077a411b243679c2ff0e8c2cb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20739 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-13sparc: Fix a warning/error in tlb.cc.Gabe Black
gcc has started to not like memseting an ojbect to zero in some cases. Cast the TlbEntry pointer to a void * before memsetting it to placate gcc. Change-Id: Iccb3c326fdb82f1f111329ff1a80bb6719cace47 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20830 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-09-06arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ic08ac1e7f3ebef408a83aa068ce15e9dfe2aa3cd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20628 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ide93464f62288fbe8f409f718487a15512c01295 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20627 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ib1691f1cba08251a36ceb959849b61c33cc3e93b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20626 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ib30c7a49490f05f88ddfd7572dd360cb92647f81 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20625 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: Add explicit AArch64 MiscReg bankingGiacomo Travaglini
Change-Id: I89836d14491a51b1573f45c8012e3ad12b107d24 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20623 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: Use same template across all MSR instGiacomo Travaglini
Change-Id: Ifb9f1db288e401761b71ccf426e370c475e5663f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20622 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: SySDC64 Instructions (CMO) using MiscRegIndexGiacomo Travaglini
Change-Id: Ia66d6abf965b1d33579e8fa048608d99c93ff2ce Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20621 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-06arch-arm: fix GDB stub after SVECiro Santilli
The SVE patches made registers longer by increasing NumVecElemPerVecReg, but the GDB XML was not updated to account for that, and as a result GDB connections were failing with: Remote 'g' packet reply is too long This commit introduces NumVecElemPerSimdVecReg which counts only the SIMD register sizes to get it back working. SVE GDB support is not added here. Change-Id: I4191b9f1999ae02b0308863db4cc9b5b16a27d6d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20468 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: SGI registers undecoded in AArch32Giacomo Travaglini
Change-Id: I64d3e639e1beaa507263637d59499aafeb5a19f8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20612 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regsGiacomo Travaglini
The readMiscReg/setMiscReg methods were not forwarding register reads/writes to the cpu interface when in AArch32. Change-Id: Ide983e793b8033a88d31fe6ea87eaeffe9b093f5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20611 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-05arch-x86: Adding warning for movntiPouya Fotouhi
We are ignoring the non-temporal hint here, and implementing this instruction as a cacheable instruction. This change adds a warning to let user know about this workaround. Change-Id: I2e40437a44282fe9cf7772a25a8870bd8729a6ed Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20428 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-22 11:16:44 +0000