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2018-03-15arch-x86,sim-se: Bump kernel version to 3.2Jason Lowe-Power
Current glibc expects at least kernel 3.2. Bump this so syscall emulation with dynamically-linked binaries works. Change-Id: I07077ed2de14c308f6ff79cae677915612557332 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8903 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-03-15arch-arm: Fix unused variable warning in faults.ccNikos Nikoleris
Change-Id: Ife4a2189e140cdefcf53fa88213d8a5225067457 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9201 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-03-15x86: Add bitfields which can gather/scatter bases and limits.Gabe Black
Add bitfields which can gather/scatter base and limit fields within "normal" segment descriptors, and in TSS descriptors which have the same bitfields in the same positions for those two values. This centralizes the code which manages those bitfields and makes it less likely that a local implementation will be buggy. Change-Id: I9809aa626fc31388595c3d3b225c25a0ec6a1275 Reviewed-on: https://gem5-review.googlesource.com/7661 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-14x86: Simplify the implementations of RDTSC and RDTSCP slightly.Gabe Black
These instructions originally read the TSC into t1 and then unpacked it into eax and edx using a move, a right shift, and then another move. We can combine the second shift and move. The shift will move the upper 32 bits into the lower 32 bits, and clear the upper 32 bits to zero. This has the same effect as moving the lower 32 bits post-shift into another register, since the upper 32 bits will be cleared to zero based on x86 partial register access semantics. Change-Id: Iba85e501c7e84147ad0047f5c555e61bdf8f032b Reviewed-on: https://gem5-review.googlesource.com/9044 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-14x86: Implement the RDTSCP instruction.Gabe Black
This is very similar to RDTSC, except that it requires all younger instructions to retire before it completes, and it writes the TSC_AUX MSR into ECX. I've added an mfence as an iniitial microop to ensure that memory accesses complete before RDTSCP runs, and added an rdval microop at the end to read the TSC_AUX value into ECX. Change-Id: I9766af562b7fd0c22e331b56e06e8818a9e268c9 Reviewed-on: https://gem5-review.googlesource.com/9043 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-14x86: Mark the RDTSC instruction as .serialize_before.Gabe Black
Change-Id: I20bf6a57ea4354aac9267845bb37b70b83d6fcde Reviewed-on: https://gem5-review.googlesource.com/9042 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-14x86: Replace the .serializing directive with .serialize_(before|after).Gabe Black
This makes it explicit which type of serialization you want, and also makes it possible to make a macroop serialize before. The old serializing directive was renamed .serialize_after in the microcode assembler, and throughout the microcode implementation, and its behavior is unchanged. More specifically, it still marks the last microop within the macroop as IsSerializing and IsSerializeAfter. The new .serialize_before directive does something similar and marks the first microop as IsSerializing and IsSerializeBefore. Change-Id: Ia53466c734c651c65400809de7ef903c4a6c3e7e Reviewed-on: https://gem5-review.googlesource.com/9041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-14arm: Fix maybe-uninitialized GCC warningsChun-Chen Hsu
GCC 7 generates maybe-uninitialized warnings at the code that updates the "dest" variables in the writeVecElem function of neon64_mem.hh file. It is because the generated code does not appropriately initialize the output variable before passing it to the writeVecElem function. This patch initializes the output variable to fix this. Change-Id: I50a8f4e456ccdcaa3db1392ec097017450c56ecb Signed-off-by: Chun-Chen Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/9121 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-14arch-arm: ERET from AArch64 to AArch32 ignore MSBsGiacomo Travaglini
The 32 most significant bits of ELR_ELx must be ignored when returning from AArch64 to AArch32. Change-Id: I412d72908997916404e16e9eeca2789a9c529e58 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8881 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-12arch-arm: Adding IPA-Based Invalidating instructionsGiacomo Travaglini
This patch introduces the TLB IPA-Based invalidating instructions in aarch32. In the entry selection policy the level of translation is not taken into account. This means that no difference stands between (e.g.) TLBIIPAS2 and TLBIPAS2L. Change-Id: Ieeb54665480874d2041056f356d86448c45043cb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8822 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-12arch-arm: Implement missing aarch32 TLBI registersGiacomo Travaglini
In the pool of TLB Invalidate system register a category of instruction was missing: the ones operating on entries added to the TLB during the last level only of a table walk. (E.g. TLBIVMAL). This patch is not considering this matching criteria when invalidating the entries and it is rather performing the invalidation on all levels. Change-Id: I5f2186cfdd73793e76c90b260f7128be187903fe Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8821 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-08sparc: Passify a new g++ warning.Gabe Black
g++ seems to think there are some missing brackets when initializing the sparc fault information. Passify it by adding extra brackets. Change-Id: I826995f88b8ac8a21721c949a244dec480831b80 Reviewed-on: https://gem5-review.googlesource.com/8763 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2018-03-08arch-arm: Enable Debug IFSC when faulting to aarch64 modeGiacomo Travaglini
Previous code was aborting simulation when a debug exception taken in aarch64 mode was encountered. This because an invalid (0xff) instruction fault status code was produced. Change-Id: I289f93f672be70cfbdc404be536809835160bdaf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8363 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-08arch-arm: Fix FSC generation in AbortFaultGiacomo Travaglini
The fault status code generated by a Prefetch/Data Fault was containing a wrong value when the fault was triggered in aarch32 but handled in aarch64. This because the encoding differs between the two ISAs and the encoder was just checking the starting ISA rather than the the ending one. In this case the getFsr must be called after we know which is the ending ISA, which happens only after ArmFault::invoke gets called. The fsc update hence happens before writing into the Syndrome register. Change-Id: I725f12b6dcc0178f608233bd3d15e466d1cd1ffc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8362 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-08arch-arm: Introduce update method in ArmFault classGiacomo Travaglini
There is a set of internal variables in ArmFault thats get updated once the fault is invoked (ArmFault::invoke). Sometimes we rely on those even if the fault is generated but not invoked (e.g. when checking if a memory access is producing a fault). This patch is moving the update functionalities inside a public method so that a client can make use of it even when not invoking the fault. Change-Id: I3ac5b6835023f28ec569fe25487dffa356e1b2fd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8361 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-08arch-arm: Fix PCAlignmentFault routing to HypervisorGiacomo Travaglini
This patch enables PCAlignmentFault routing to Hypervisor in case HCR_EL2.TGE == 1, as is happening for other arm exceptions. Change-Id: I48364ef1a0bcb5d030135221ae4bc6429e32759e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8841 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-06scons: Switch from the print statement to the print function.Gabe Black
Starting with version 3, scons imposes using the print function instead of the print statement in code it processes. To get things building again, this change moves all python code within gem5 to use the function version. Another change by another author separately made this same change to the site_tools and site_init.py files. Change-Id: I2de7dc3b1be756baad6f60574c47c8b7e80ea3b0 Reviewed-on: https://gem5-review.googlesource.com/8761 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-06arm: Remove ignored const qualifierSiddhesh Poyarekar
gcc8 warns about ignored const qualifiers (-Wignored-qualifiers) and that breaks builds. It was suggested that the warning be moved to Wextra[1] but that's probably not going to happen anytime soon. [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82711 Change-Id: Ib808906deb9a1c2dccb1c34b6563db0c24c66655 Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/8562 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-24sparc: Fix FS Checkpoint loadingKhalique
Proposed changes to SPARC FS simulation, testing indicates that checkpoints are now loaded correctly with the following command: build/SPARC/gem5.opt configs/example/fs.py -r 1 Change-Id: Icd44f01a74c41a78828ef6fd7b661e584bdb6966 Reviewed-on: https://gem5-review.googlesource.com/8581 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-02-20arch-arm: Make hlt64 a mem barrier with semihostingGiacomo Travaglini
The HLT instruction is used to trap into semihosting. The semihosting code can change the contents of memory behind the back of the CPU, which requires instructions triggering semihosting to be non-speculative and memory barriers. Change-Id: I735166251aa194120ad49c08082d4ac65fe96524 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8373 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-20arch-arm: Add AArch32 HLT Semihosting interfaceGiacomo Travaglini
AArch32 HLT instruction is now able to issue Arm Semihosting commands as the AArch64 counterpart in either Arm and Thumb mode. Change-Id: I77da73d2e6a9288c704a5f646f4447022517ceb6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8372 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-20arch-arm: Add AArch32 SVC Semihosting interfaceGiacomo Travaglini
AArch32 Svc instruction is now able to issue Arm Semihosting commands as the AArch64 counterpart in either Arm and Thumb mode. Change-Id: Ibe47ac23d0c26f3f819cc0e2b3ee874b5cdbb3d3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8371 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-20arch-arm: Adding isa templates for semihosting opsGiacomo Travaglini
A new class of Semihosting constructor templates has been added. Their main purpose is to check if the Exception Generation Instructions (HLT, SVC) are actually a semihosting command. If that is the case, the IsMemBarrier flag is raised, so that in the O3 model we perform a coherent memory access during the semihosting operation. Change-Id: Ib87fdeb70ee7a930659563230a80cce0e1372c32 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8370 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-20arch-arm: HLT using immediate when checking for semihostingGiacomo Travaglini
HLT can use the immediate field when checking for semihosting, rather than re-parsing it from the machInst variable. Change-Id: I072cb100029da34d129b90c5d17e1728f9016c88 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8369 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-20arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassemblyGiacomo Travaglini
This patch fixes the disassembly of AArch64 Exception Generating instructions, which were not printing the encoded immediate field. This has been accomplished by changing their underlying type to a newly defined one. Change-Id: If58ae3e620d2baa260e12ecdc850225adfcf1ee5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8368 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-19arch-riscv: Fix compressed branch op offsetAlec Roelke
There is a bug in RISC-V's compressed branch instructions where the offsets are not stored in ImmOp's immediate field, causing incorrect branchTarget() return values. This patch adds a new compressed branch op format, CBOp, which correctly stores the offset. Change-Id: Iac6e9b091d63f3dce4717ee5a9ec31a7cbd6c377 Reviewed-on: https://gem5-review.googlesource.com/8441 Reviewed-by: Tuan Ta <qtt2@cornell.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-02-19arch-arm: Semihosting not available in syscall emulationGiacomo Travaglini
Arm Semihosting is not available in syscall emulation since we don't have an Arm system in that scenario. Trying to use it in "se" mode will make getArmSystem assertion fail. Change-Id: I4cf49ae801ec6e6c93134ac6ae2a0f412040684c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8367 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-19arch-arm: Add support for secure state in semihostingAndreas Sandberg
The semihosting component currently issues non-secure memory accesses using the standard port proxy. This doesn't work when the guest is running in secure state. Change-Id: Id34b142cfcd9d77b455c040ae7f7397c29aebbc6 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8365 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-19arch-arm: Add aarch64 semihosting supportAndreas Sandberg
Add basic support for Arm Semihosting 2.0 simulation calls [1]. These calls let the guest system call a simulator or debugger to request OS-like support when running bare metal code. With the exception of SYS_SYSTEM, this implementation supports all of the Semihosting 2.0 specification in aarch64. [1] https://developer.arm.com/docs/100863/latest/preface Change-Id: I08c153c18a4a4fb9f95d318e2a029724935192a7 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8147 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-16arch-arm: IMPLEMENTATION DEFINED registerGiacomo Travaglini
A new pseudo register has been added to the Misc pool. It is the implementation defined register. This kinds of registers are covered by the architecture and must be treated differently than UNIMPLEMENTED registers: their access can be trapped to EL2 (See HCR.TIDCP bit in the arm arm). Some previously undecoded registers in c9,c10,c11 have now this register type. Change-Id: Ibfc35982470b9dea0ecf39aaa6b1012a21852f53 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7922 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-16arch-arm: Arch regs and pseudo regs distinctionGiacomo Travaglini
A new identifier has been introduced: NUM_PHYS_MISCREGS, which is used as a boundary for the number of physical (real) Misc registers in the system. Pseudo registers (like CP15_UNIMPL) have been moved after the NUM_PHYS_MISCREGS identifier, so that their enum number is (NUM_PHYS_MISCREGS < number < NUM_MISCREGS). Moving away those registers has created some free slots that can be used for future Misc register implementation. SERIALIZE and UNSERIALIZE now only save/restore PHYSICAL Misc Registers. This allows us to define as many pseudo registers as we want without being concerned about checkpoint compatibility. Change-Id: I7e297b814eeaa4bee640e81bee625fb66710af45 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7921 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-16arch-arm: Fix syntax error in TLB::getResultTeChuan Zhu
The patch fixes one syntax error in TLB::getResultTe Change-Id: I31a72a52d5c03f43929a69ca1be61d9c20e76f5b Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7983 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-16arch-arm: Fix big endian support in {Load,Store}Double64Chuan Zhu
{Load, Store}Double64 didn't consider some of the big-endian situations. Added big-endian related data conversions to correct them. Change-Id: I8840613f94446e6042276779d1f02350ab57987f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8145 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-16arch-arm: Fix big endian support in do{Long,L1,L2}DescriptorChuan Zhu
do{Long,L1,L2}Descriptor was not able to load descriptors correctly for big-endian situations, causing recognised Descriptors. Added big-endian related data conversions to correct them. Change-Id: I0fdfbbdf56f94bbed19172acae1b6e4a0382b5a0 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8144 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-16arch-arm: Add support for automatic reset addr selectionAndreas Sandberg
Add an option to automatically set the aarch64 reset vector to the entry point of the kernel. This is useful when running bare metal workloads that don't use a normal boot loader. Change-Id: Id472f865d461f0d8d8ea8efe5db582c170de0b90 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8143 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-16arch-arm: Change ArmFault cast from reinterpret to staticGiacomo Travaglini
Changing casting type in src/arch/arm/isa.cc Change-Id: Ia19b30a1bf8b1b25df149b52613a3533eaced03a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8241 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-16arch-arm: Decode Brk64 instructionsAndreas Sandberg
The brk instruction in aarch64 was decoded as an unimplemented instruction. Fix that. Change-Id: I3eb36a016ab56d882426c5cdef3a0b594de0f9cd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8142 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-16arch-arm: Fix Secure state check in checkFPAdvSIMDTrap64Chuan Zhu
The old code does secure state check by using "el <= EL2", which mis-considers secure EL1 and EL0. This patch fixes this by using inSecureState as in ARM ARM. Change-Id: I01d847c6af022c1462b16206cbc576f15f5569fd Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8081 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-13sim: Make Stats truly non-copy-constructibleRekai Gonzalez-Alberquilla
The stats are silently non-copy constructible. Therefore, when someone copy-constructs any object with stats, asserts happen when registering the stats, as they were not constructed in the intended way. This patch solves that by explicitly deleting the copy constructor, trading an obscure run-time assert for a compile-time somehow more meaningful error meassage. This triggers some compilation errors as the FaultStats in the fault definitions of ARM and SPARC use brace-enclosed initialisations in which one of the elements derives from DataWrap, which is not copy-constructible anymore. To fix that, this patch also adds a constructor for the FaultVals in both ISAs. Change-Id: I340e203b9386609b32c66e3b8918a015afe415a4 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8082 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-09sim: Remove _numContexts member in System classGiacomo Travaglini
A System object has a _numContexts member variable which represent the number of ThreadContext registered in the System. Since this has to match the size of the ThreadContext vector, this patch removes the manually cached size. This was usually used as a for-loop index, whereas we want to enforce the use of range-based loops whenever possible. Change-Id: I1ba317c0393bcc9c1aeebbb1fc22d7b2bc2cf90c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8062 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-02-08arch-arm: Correct SecureMonitorTrap vals for aarch32Giacomo Travaglini
This patch replaces the dummy values which were defined for the SecureMonitorTrap thus enabling its usage in aarch32 mode. 1) It changes the vector table offset from 0x14 to 0x4 in compliance with the armv8 documentation. 2) When trapping in monitor mode for aarch32, the mon_lr is updated with the pc + a non zero offset (+4/2 depending on the current instruction set: +4 for A32, +2 for T32). Change-Id: I01e1e52bf5ecd405e7472e31e01cf9a599153b08 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8041 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-08arch-arm: Fixed error in choosing vector offsetChuan Zhu
The old code chose vector offset associated with exceptions taken to EL3 by incorrectly using "from64", which is associated with the exception level where the exception was taken from. However, the offset should depends on the ISA of the lower EL and not of the starting EL itself, as specified in ARM ARM. This patch corrects this by implementing the method in AArch64.TakeException in ARM ARM. Change-Id: I8f7c9aa777c5f2eef9e2d89c36e9daee23f3a822 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8001 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-08arch-arm: Don't change PSTATE in Illegal Exception returnGiacomo Travaglini
This patch fixes the Illegal Exception return handler. According to the armarm documentation, when PSTATE.IL is set to one because of an illegal exception return, PSTATE.{EL, nRW, SP} are unchanged. This means the Exception level, Execution state, and stack pointer selection do not change as a result of the return. Change-Id: I35f2fe68fb2822a54fc4a21930871eab7a1aaab4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8021 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-08arch-arm: Handle route to EL2 in Supervisor TrapChuan Zhu
Supervisor Trap is supposed to be able to handle exceptions routed to EL2, which is enabled by HCR_EL2.TGE. This fix adds routeToHyp() function to Supervisor Trap to handle this, similar to that in UndefinedFault, DataAbort, etc. Change-Id: I1fcf9f2d445ecbc13c8f6d3b7d599728b0250ab7 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7961 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Change the type of fault for dc ivac instructionsNikos Nikoleris
Change-Id: I00f957a3bc4721a66db62b1257f10e9019a94608 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7829 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-07arch-arm: Unify permission checks for dc * instructionsNikos Nikoleris
Change-Id: Ib47f4134e3f0a580e5356d384a5d3b293c1af7be Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7828 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Check cache maintenance insts for permission faultsNikos Nikoleris
In AArch32, data cache maintenance instructions that operate by VA do not generate permission faults. In AArch64, a data cache invalidate instruction can generate a permission fault when there are no write permissions to the specified VA. Data cache clean and data cache clean and invalidate instructions do not generate permission faults. Checks for external aborts are also bypassed for data cache maintenance instructions. Change-Id: Iea5bc665e4cf66d528e36b671535b66637c4b224 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7827 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Turn dc ivac to dc civac when some conditions are metNikos Nikoleris
The Arm ARM defines that at EL1 a data cache invalidate instruction performs a data cache clean and invalidate operation if all of the following apply: * EL2 is implemented, * HCR_EL2.VM is set to 1, * SCR_EL3.NS is set to 1 or EL3 is not implemented. This changeset implements this behavior. Change-Id: I6b6aef2f4b1e7eb107c069fdb0a10f4aa8e6b196 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7826 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-07arch-arm: Fix printing of the data cache maintenance instructionsNikos Nikoleris
Change-Id: I2322c7bf65b38cb07a1ea2b5dc25dfc5a0496cf0 Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7825 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-07arch-arm: Fix cache line size for cache maintenace instNikos Nikoleris
Cache maintenance operations operate on whole cache blocks. This changeset uses the system cache line size as the size of the cache maintenance requests and masks the lower bits of the effective address. Change-Id: I6e7aefff51670c8cac39e4e73db21a0c5a0b7aef Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7824 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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