| Age | Commit message (Expand) | Author |
|---|
| 2019-10-16 | arch,base,sim: Move Process loader hooks into the Process class. | Gabe Black |
| 2019-10-15 | x86: Use a std::function to handle MSI completion. | Gabe Black |
| 2019-10-15 | arch,base: Restructure the object file loaders. | Gabe Black |
| 2019-10-15 | arch-x86: Make LFENCE a serializing instruction | Isaac Richter |
| 2019-10-15 | x86: De-x86ify the IntMasterPort. | Gabe Black |
| 2019-10-14 | x86: Simplify and consolidate the code that assembles an MSI on x86. | Gabe Black |
| 2019-10-14 | fastmodel: Expose all CPU communication ports from the GIC. | Gabe Black |
| 2019-10-12 | x86: Stop using and delete the x86 IntDevice class. | Gabe Black |
| 2019-10-12 | arch,base: Separate the idea of a memory image and object file. | Gabe Black |
| 2019-10-10 | arch,base: Stop loading the interpreter in ElfObject. | Gabe Black |
| 2019-10-10 | arch-arm: Move generateDtb to ArmSystem | Giacomo Travaglini |
| 2019-10-10 | dev-arm, configs: Remove RealViewPBX platform | Giacomo Travaglini |
| 2019-10-10 | arch, base: Stop assuming object files have three segments. | Gabe Black |
| 2019-10-09 | fastmodel: Export GICV3Comms directly. | Gabe Black |
| 2019-10-09 | arch-mips,arch-riscv,base: Get rid of the unused HexFile class. | Gabe Black |
| 2019-10-09 | base: Rename Section to Segment, and some of its members. | Gabe Black |
| 2019-10-08 | base: Get rid of the unused global pointer in object files. | Gabe Black |
| 2019-10-07 | fastmodel: Make CortexA76x1's interrupts use gem5's mechanisms. | Gabe Black |
| 2019-10-07 | kvm, arm: fix the size of MISCREG_FPSR and MISCREG_FPCR | Ciro Santilli |
| 2019-10-03 | arch-arm: Annotate CM flag in AA64 CM Instructions | Giacomo Travaglini |
| 2019-10-03 | arch-arm: Set CM bit in DataAbort | Giacomo Travaglini |
| 2019-10-02 | arch-arm: Create helper for sending events (SEV) | Giacomo Travaglini |
| 2019-10-02 | fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU. | Gabe Black |
| 2019-10-02 | fastmodel: Implement a custom sendFunctional for CortexA76x1. | Gabe Black |
| 2019-10-02 | x86: Switch from MessageReq and Resp to WriteReq and Resp. | Gabe Black |
| 2019-10-02 | fastmodel: Let the EVS set an attribute for getSendFunctional to return. | Gabe Black |
| 2019-10-01 | fastmodel: Add a gem5Cpu attribute to the CortexA76x1. | Gabe Black |
| 2019-10-01 | fastmodel: Add a utility class which makes it easier to watch signals. | Gabe Black |
| 2019-10-01 | fastmodel: Pull out and simplify the interrupt mechanism in the GIC. | Gabe Black |
| 2019-09-27 | fastmodel: Add glue code which adapts fastmodels to run in gem5. | Gabe Black |
| 2019-09-23 | cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor> | Jordi Vaquero |
| 2019-09-21 | x86: Templatize the IntMasterPort. | Gabe Black |
| 2019-09-21 | x86: Templatize IntSlavePort. | Gabe Black |
| 2019-09-21 | x86: Turn the local APIC into a PioDevice instead of a BasicPioDevice. | Gabe Black |
| 2019-09-20 | arch-x86: ignore non-temporal hint for movntps/movntpd SSE insts | Pouya Fotouhi |
| 2019-09-19 | arch-x86: Change warn to warn_once for NT instructions | Hoa Nguyen |
| 2019-09-19 | arch-arm: PSTATE.PAN changes should inval cached regs in TLB | Giacomo Travaglini |
| 2019-09-18 | arch-arm: Fix Data Abort ISS when caused by Atomic operation | Giacomo Travaglini |
| 2019-09-18 | arch-arm: ISV bit in DataAbort should check for translation stage | Giacomo Travaglini |
| 2019-09-18 | arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2.E2H=1 | Giacomo Travaglini |
| 2019-09-18 | arch, x86: Rework the debug faults and microops. | Gabe Black |
| 2019-09-13 | sparc: Fix a warning/error in tlb.cc. | Gabe Black |
| 2019-09-06 | arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 banking | Giacomo Travaglini |
| 2019-09-06 | arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 banking | Giacomo Travaglini |
| 2019-09-06 | arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 banking | Giacomo Travaglini |
| 2019-09-06 | arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking | Giacomo Travaglini |
| 2019-09-06 | arch-arm: Add explicit AArch64 MiscReg banking | Giacomo Travaglini |
| 2019-09-06 | arch-arm: Use same template across all MSR inst | Giacomo Travaglini |
| 2019-09-06 | arch-arm: SySDC64 Instructions (CMO) using MiscRegIndex | Giacomo Travaglini |
| 2019-09-06 | arch-arm: fix GDB stub after SVE | Ciro Santilli |
