gem5 - gem5

Age	Commit message (Expand)	Author
2019-10-02	x86: Switch from MessageReq and Resp to WriteReq and Resp.	Gabe Black
2019-10-02	fastmodel: Let the EVS set an attribute for getSendFunctional to return.	Gabe Black
2019-10-01	fastmodel: Add a gem5Cpu attribute to the CortexA76x1.	Gabe Black
2019-10-01	fastmodel: Add a utility class which makes it easier to watch signals.	Gabe Black
2019-10-01	fastmodel: Pull out and simplify the interrupt mechanism in the GIC.	Gabe Black
2019-09-27	fastmodel: Add glue code which adapts fastmodels to run in gem5.	Gabe Black
2019-09-23	cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>	Jordi Vaquero
2019-09-21	x86: Templatize the IntMasterPort.	Gabe Black
2019-09-21	x86: Templatize IntSlavePort.	Gabe Black
2019-09-21	x86: Turn the local APIC into a PioDevice instead of a BasicPioDevice.	Gabe Black
2019-09-20	arch-x86: ignore non-temporal hint for movntps/movntpd SSE insts	Pouya Fotouhi
2019-09-19	arch-x86: Change warn to warn_once for NT instructions	Hoa Nguyen
2019-09-19	arch-arm: PSTATE.PAN changes should inval cached regs in TLB	Giacomo Travaglini
2019-09-18	arch-arm: Fix Data Abort ISS when caused by Atomic operation	Giacomo Travaglini
2019-09-18	arch-arm: ISV bit in DataAbort should check for translation stage	Giacomo Travaglini
2019-09-18	arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2.E2H=1	Giacomo Travaglini
2019-09-18	arch, x86: Rework the debug faults and microops.	Gabe Black
2019-09-13	sparc: Fix a warning/error in tlb.cc.	Gabe Black
2019-09-06	arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 banking	Giacomo Travaglini
2019-09-06	arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 banking	Giacomo Travaglini
2019-09-06	arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 banking	Giacomo Travaglini
2019-09-06	arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking	Giacomo Travaglini
2019-09-06	arch-arm: Add explicit AArch64 MiscReg banking	Giacomo Travaglini
2019-09-06	arch-arm: Use same template across all MSR inst	Giacomo Travaglini
2019-09-06	arch-arm: SySDC64 Instructions (CMO) using MiscRegIndex	Giacomo Travaglini
2019-09-06	arch-arm: fix GDB stub after SVE	Ciro Santilli
2019-09-06	arch-arm: SGI registers undecoded in AArch32	Giacomo Travaglini
2019-09-06	arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regs	Giacomo Travaglini
2019-09-05	arch-x86: Adding warning for movnti	Pouya Fotouhi
2019-09-05	arch-x86: implement movntq/movntdq instructions	Pouya Fotouhi
2019-08-30	arm,kvm: Fix python imports from global namespace	Giacomo Travaglini
2019-08-28	mem: Eliminate the Base(Slave\|Master)Port classes.	Gabe Black
2019-08-23	arch-riscv: fix GDB register cache	Alec Roelke
2019-08-21	arch-riscv: Update register file	Yifei Liu
2019-08-21	arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0	Ciro Santilli
2019-08-21	arch-arm: Fix implicit fallthrough build errors	Chun-Chen TK Hsu
2019-08-20	arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currEL	Giacomo Travaglini
2019-08-20	arch-arm: Replace direct use cpsr.el with currEL helper	Giacomo Travaglini
2019-08-20	arch-arm: Overload currEL helper with CPSR argument	Giacomo Travaglini
2019-08-20	arch-arm: Rewrite the currEL helper method to use opModeToEL	Giacomo Travaglini
2019-08-16	x86: Stop CPUID from claiming we support xsave.	Gabe Black
2019-08-15	x86: Make unsuccessful CPUID instructions zero the result.	Gabe Black
2019-08-12	arch-arm: Added LD/ST<op> atomic instruction family and SWP instrs	Jordi Vaquero
2019-08-12	arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func	Jordi Vaquero
2019-08-10	x86: Move some fixed or dummy config information into X86LocalApic.py.	Gabe Black
2019-08-09	arch: Bump MaxVecRegLenInBytes to 4096	Tony Gutierrez
2019-08-07	arch-arm: Add TypeAtomicOp class to be used by new atomic instructions	Jordi Vaquero
2019-08-07	arch-arm: adding register control flags enabling LSE implementation	Jordi Vaquero
2019-08-06	sim-se: add new getpgrp system call	Brandon Potter
2019-08-06	sim-se: adding pipe2 syscall	Matthew Sinclair