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AgeCommit message (Expand)Author
2019-05-03arch-riscv,isa: Fix for compressed jump (c_j) immAvishai Tvila
2019-04-30arch: Stop using TheISA within the ISAs.Gabe Black
2019-04-30x86: Get rid of some unnecessary TheISA-es in x86.Gabe Black
2019-04-30sparc: Move translation constants from isa_traits.hh into tlb.hh.Gabe Black
2019-04-30sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.Gabe Black
2019-04-30arch: Remove the mt.hh switching header.Gabe Black
2019-04-30cpu: alpha: Delete all occurrances of the simPalCheck function.Gabe Black
2019-04-30alpha: Implement simPalCheck within the ISA description.Gabe Black
2019-04-30cpu: Remove hwrei from the generic interfaces.Gabe Black
2019-04-30arch: cpu: Track kernel stats using the base ISA agnostic type.Gabe Black
2019-04-30alpha: Implement HWREI in the ISA.Gabe Black
2019-04-30alpha: Add some control registers to the ISA operands list.Gabe Black
2019-04-29mips: Implement readRegOtherThread and setRegOtherThread directly.Gabe Black
2019-04-29arch-arm: Faults DebugFlag now printing inst opcode if availableGiacomo Travaglini
2019-04-29arch-arm: Report real instruction encoding when UndefinedGiacomo Travaglini
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
2019-04-28mem: Remove the ISA specialized versions of port proxy's read/write.Gabe Black
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-04-26arch-arm: updateMiscReg not setting isHyp in aarch64Giacomo Travaglini
2019-04-26arm: Factor some repetition out of the ProcessInfo constructor.Gabe Black
2019-04-25arm: Fix some style issues in stacktrace.cc.Gabe Black
2019-04-25x86: Refactor the ProcessInfo constructor.Gabe Black
2019-04-25x86: Fix some style issues in stacktrace.cc.Gabe Black
2019-04-25arch-arm: Remove un-needed hyp flag in TLBI operationsGiacomo Travaglini
2019-04-25arch-arm: Correct target EL field in TLBI operationsGiacomo Travaglini
2019-04-22sim-se: Enhance clone for X86KvmCPUAlexandru Dutu
2019-04-22cpu: Eliminate the ProxyThreadContext class.Gabe Black
2019-04-11arch-arm: Enable PMSELR_EL0 read in PMUGiacomo Travaglini
2019-04-03misc: Removed inconsistency in O3* debug msgsAndrea Mondelli
2019-04-02dev-arm: Make GICv3 maintenance interrupt an ArmInterruptGiacomo Travaglini
2019-04-01dev-arm: Correct cast of template parameterAndrea Mondelli
2019-03-28arch-arm: Fix use of bitwise operators on booleansJavier Setoain
2019-03-28arch-arm: Fix index generation for VecElem operandsGiacomo Travaglini
2019-03-25arch-arm: Add missing fall-through defaultsJavier Setoain
2019-03-25arch-power: Rename program counter registersSandipan Das
2019-03-25arch-power: Simplify doubleword operand typesSandipan Das
2019-03-22sim-se: Fixed initialization array sizeTiago Muck
2019-03-21dev-arm: ambiguous use of getPort()Andrea Mondelli
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2019-03-14arch-arm,cpu: Add initial support for Arm SVEGiacomo Gabrielli
2019-03-11arch-hsail: changed gen.py shebang from python(3) to python2.7Ryan Gambord
2019-03-11arch-arm: Fixing implicit fallthrough build errorsRyan Gambord
2019-03-01mem-cache: alias to mem::getMasterPort in TLB classAndrea Mondelli
2019-03-01arch-arm: implement floating point aarch32 VCVTA familyCiro Santilli
2019-02-23python: Enforce absolute imports for Python 3 compatibilityAndreas Sandberg
2019-02-20x86: Call the base class's regStats in X86ISA::TLBBagus Hanindhito
2019-02-18arch-generic: Making base TLB class a MemObjectIvan Pizarro
2019-02-18arch-arm: Move GICv3 detection at startup timeGiacomo Travaglini
2019-02-13sim-se: update the arm kernel versionAyaz Akram
2019-02-12python: Replace dict.has_key with 'key in dict'Andreas Sandberg