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2019-08-05arch-arm: Rewrite MSR immediate instruction classGiacomo Travaglini
MSR <pstatefield>, #imm is used for setting a PSTATE field using an immediate. Current implementation has the following flaws: * There is no base MSR immediate definition: all the existing PSTATE fields have a different class definition * Those implementation make use of a generic data64 base class which results in a wrong disassembly (pstate register is printed as an integer register). This patch is fixing this by defining a new base class (MiscRegImmOp64) and new related templates. In this way, we aim to ease addition of new PSTATE fields (in ARMv8.x) Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-27arch-arm: Fix reg dependency for SVE gather microopsGabor Dozsa
The first microop of an SVE gather creates a copy of the source vecreg into AA64FpUreg0. The subsequent microops must refer to this copy as a source in order to establish the correct register dependencies. Change-Id: I84d8c331f9f9ebca609948a15f686a7cde67dc31 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19172 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-27arch-arm: Fix tracing code for SVE gatherGabor Dozsa
Printing the entire contents of the dest vecreg for each gather microop is suboptimal as it creates false positive differences between Atomic and O3 traces. This fix prints only the memory data which a microop loads from memory. Change-Id: Idd8e0b26a96f9c9cc0b69360174bedf6a9f6dcb5 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19171 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-27arch-arm: Add SVE LD1RQ[BHWD]Javier Setoain
Add both scalar+scalar and scalar+immediate versions. Change-Id: If5fa1a71ab0dab93f9d35b544ea0899ece858bea Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19170 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-27arch-arm: Fix decoding for SVE memory instructionsAdrià Armejach
Some SVE memory instructions are missing the makeSP function for register operands that can be the SP register. This leads to segmentation faults on the application side as the wrong register is decoded. Change-Id: Ic71abc845e0786a60d665231b5f7b024d2955f4b Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19169 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-07-27arch-arm: Add support for SVE load/store structuresJavier Setoain
Change-Id: I4d9cde18dfc3d478eacc156de6a4a9721eb9e2ff Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13524 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-22arch-x86: Don't free PTW state with inflight requestsMatthew Poremba
If a page table walk is squashed, the walker state is being deleted in the squash code. If there are in flight requests, the deleted walker state values may be clobbered, leading to undefined behavior. This adds a squashed boolean to the walker state which is set if a walk is squashed while requests are still in flight. When packets for the in flight request return, we check if the walk was squashed and return that the walk is complete once the number of in flight requests reaches zero. The walker state is then freed by the PTW. Change-Id: I57a64b1548b83a8a9e8441fc9d6f33e9842df2b3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19568 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-19arch-arm: Implement ARMv8.1-HPD, Hierarchical permission disableGiacomo Travaglini
According to the armarm: ARMv8.1-HPD introduces the facility to disable the hierarchical attributes, APTable, PXNTable, and UXNTable, in the translation tables. This disable has no effect on the NSTable bit. This feature is mandatory in ARMv8.1 implementations. This feature is added only to the VMSAv8-64 translation regimes. ARMv8.2 extends this to the AArch32 translation regimes, see ARMv8.2-AA32HPD. The ID_AA64MMFR1_EL1.HPDS field identifies the support for ARMv8.1-HPD. Change-Id: Ibbf589b82f2c1e4437b43252f8f633e8f6fb0b80 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19610 Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-19arch-arm: Add HPD bit for TCR_EL2/EL3Giacomo Travaglini
This is controlling Hierarchical Permissions for EL3 and for EL2 when HCR_EL2.E2H = 0. Change-Id: I9d6615ff4980cc56a28dc32088cf1524155f0fa4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19609 Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-19arch-arm: Clean Fault generation when processing Long DescriptorGiacomo Travaglini
A new shared method has been introduced: generateLongDescFault Change-Id: I7eb6fa1347a6c2cf9cb11fd9f2137d983c4f7a40 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19608 Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-18arch-arm: Add first-/non-faulting load instructionsGabor Dozsa
First-/non-faulting loads are part of Arm SVE. Change-Id: I93dfd6d1d74791653927e99098ddb651150a8ef7 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19177 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-17arch-arm: Use ExceptionLevel type in TlbEntryGiacomo Travaglini
Replacing uint8_t with ExceptionLevel type in the arm TlbEntry. The variable is representing the translation regime it is targeting. Change-Id: Ifcd6e86c5d73f752e8476a2b7fda9ea74a0c7a3b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19488 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-16arch-x86: add unconditional tag to calls/returnsHoa Nguyen
The branch predictor checks whether an instruction is unconditional branch before adding it or checking the RAS. With this change, the RAS is significantly more effective for short running x86 workloads. Change-Id: I60af5f2f583b898ad77f79f4b0478d6cda88fc21 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19448 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2019-06-26arch, arm: Update miscRegs in getTEAnouk Van Laer
Normally, a translation will start via translateTiming/functional which will check if the miscRegs have been updated and if so, will update the TLB state accordingly. However, in a 2 stage system, if there is a hit in stage 1, the resulting IPA will be sent to the S2-TLB for translation via a getTE() function call (via the stage2_lookup object). This will cause the state of the S2-TLB to be out of sync. Change-Id: I117e4032fc76d7d31f4f999887b5573a7e5811e6 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14995 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-06-17arch-arm: Move the memacc_code before op_wb in fp loadsGiacomo Travaglini
This is trying to fix the bug that arises when a memory exception is generated during a fp flavoured load (A memory load targeting a SIMD & FP register). With the previous template a fault was not stopping the register value to be modified (wrong) if (fault == NoFault) { fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); %(memacc_code)s; } if (fault == NoFault) { %(op_wb)s; } The patch introduces a Load64FpExecute template which is moving the register write (memacc_code) just before the op_wb Change-Id: I1c89c525dfa7a4ef489abe0872cd7baacdd6ce3c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19228 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-10arch-arm: implement VMINNM scalar thumbCiro Santilli
VMINNM was implemented at Iabbbca2932557cf6c98ce36690c385c3ddf39ed8 but the thumb scalar encoding was missing. This patch implements it. Change-Id: Ia29ec77dbd82f6be6b3d040a0e737794f52c33bf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19108 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-07arch-arm: Fix WalkerState,Descriptors default constructorGiacomo Travaglini
Those POD strutures are not initializing all members at construction. This could lead to undefined behaviour Change-Id: Iaa8afb126382b6bfbef686883a026262f24d5ca1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Javier Setoain <javier.setoain@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19149 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-31x86: fix movsd bug on %xmm registerBrandon Potter
The movsd instruction should zero out half the register, but does not do it. This changeset adds the necessary microop to the instruction to cause correct behavior. Change-Id: I5278da3634c78a97ed0586f687a36c6dc5a34c60 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19068 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-31arm: Fix decoding of CRC32 instructions in thumb32Chun-Chen TK Hsu
The CRC32 and CRC32C instructions are incorrectly decoded in thumb32 mode according to the latest manual: https://developer.arm.com/docs/ddi0597/latest/top-level-encodings-for-t32/16-bit#dpint_2r Change-Id: I9c6684f1ec7fe14d3b4cdf13f117a9819e046578 Signed-off-by: Chun-Chen TK Hsu Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19028 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-31arch-arm: Treat SVE prefetch instructions as no-opsGiacomo Gabrielli
Change-Id: Ife0424e274dd65d6dc4f6e5cc5e37d17b03be0d8 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13522 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-30arch-arm: Add initial support for SVE gather/scatter loads/storesGiacomo Gabrielli
Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13521 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-30arch: Add include guards to auto-gen. decode headerGiacomo Gabrielli
Change-Id: I03bfc9035b82bc1a42e799cf645d43cb5dafb4cb Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18911 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-30arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.Gabe Black
These two functions were performing the same function but had two different names for historical reasons. This change merges them together, keeping the getVirtProxy name to be consistent with the getPhysProxy method used to get a non-translating proxy port. Change-Id: Idd83c6b899f9343795075b030ccbc723a79e52a4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18581 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-30arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s.Gabe Black
Al(most) all of the interesting differences between the two classes have been removed. There are some control methods which are still specific to each type which may require treating them as their true type, but most code that consumes them doesn't need to worry about which is which. Change-Id: Ie592676f1e496c7940605b66e55cd7fae18e59d6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18577 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-30arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.Gabe Black
This expands those functions into code which extracts the virt proxy and then uses the appropriate method on it. This has two benefits. First, the Copy* functions where mostly redundant wrappers around the methods the proxy port already had. Second, using them forced a particular port which might not actually be what the user wanted. Change-Id: I62084631dd080061e3c74997125164f40da2d77c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18575 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-29sim-se: add a release parameter to Process.pyCiro Santilli
Set the default release to that single value for all ISAs. glibc has checks for the kernel version based on uname, and refuses to start any syscall emulation programs if those checks don't pass with error: FATAL: kernel too old The ideal solution to this problem is to actually implement all missing system calls for the required kernel version and bumping the release accordingly. However, it is very hard to implement all missing syscalls and verify compliance. Previously, we have simply bumped the version manually from time to time when major glibc versions started breaking. This commit alleviates the problem in two ways. Firstly, having a single kernel version for all versions means that it is easier to bump all versions at once. Secondly, it makes it is possible to set the release with a parameter, which in turn can be set from the command line with: se.py --param 'system.cpu[:].workload[:].release = "4.18.0"' Change-Id: I9e3c31073bfe68735f7b0775c8e299aa62b98222 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17849 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18572 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-29arm, mem: Move the SecurePortProxy subclass into it's own file.Gabe Black
The idea of a "secure" memory area/access is specific to ARM and shouldn't be in the common mem directory, although it's built in to the generic memory protocol at this point. Regardless, it should minimially be in its own file like the virtual and physical port proxy classes are. Change-Id: I140d4566ee2deded784adb04bcf6f11755a85c0c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18569 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-24arch-arm: Fix fallthrough when trapping at EL2Giacomo Travaglini
This had been caused by the introduction of GICv3 registers trapping in commit 32a23114c14cebc5ec0067ac739144b50e412219 Change-Id: I5073e2891f3ff5c5a9e05d3456dad6f4f8ffba0d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18909 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-23arch-arm: Trap virtual accesses to GICv3 SGI registersGiacomo Travaglini
According to GICv3 documentation, a virtual write (which means HCR.IMO/FMO = 1) to ICC_SGI0R_EL1, ICC_SGI1R_EL1, ICC_ASGI1R_EL1 should trap to EL2. Change-Id: Ie7a952c2ff08590bb0c6e3854df567d714c2dc94 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17990 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-23arch-arm: Expose haveGicv3CPUInterface to the ISA interfaceGiacomo Travaglini
Change-Id: I36232b7618ad875983f34b741c51f12ddb9ae166 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17989 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-23arch-arm: Change mcrMrc15TrapToHyp signatureGiacomo Travaglini
This patch is moving MiscRegs reading inside the mcrMrc15TrapToHyp helper function. Rather than passing registers as arguments, we are just passing a ThreadContext pointer Change-Id: I6636dd3a4f92f757479d8a8d2c47de050a0b9eae Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17988 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-22sim-se: remove comment for code that movedBrandon Potter
The page table code must have moved from this class, because the comment no longer accurately reflects upon any of the surrounding code. Change-Id: If08a4298c1237a541d9875ddeaf3d3ecfd98e9db Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12300 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-05-21sim-se: change syscall function signatureBrandon Potter
The system calls had four parameters. One of the parameters is ThreadContext and another is Process. The ThreadContext holds the value of the current process so the Process parameter is redundant since the system call functions already have indirect access. With the old API, it is possible to call into the functions with the wrong supplied Process which could end up being a confusing error. This patch removes the redundancy by forcing access through the ThreadContext field within each system call. Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12299 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-20x86: Add an object file loader for linux.Gabe Black
Change-Id: I283dd1f52fd020ad3c226eb00fc9216ee034c67f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18630 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-20sparc: Add an object file loader for linux and solaris.Gabe Black
Change-Id: I76bcbc06714f7d538f03a8311994a868de3640f1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18629 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-20riscv: Add an object file loader for linux.Gabe Black
Change-Id: I3accca91cc4e02fa8e3a1169590cbe6696cf05e2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18628 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2019-05-20power: Add an object file loader for linux.Gabe Black
Change-Id: I64ce81e98a6dc96754554d0fdcd7d16b8a2752d4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18587 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>
2019-05-20mips: Add an object file loader for linux.Gabe Black
Change-Id: Icae6430a210076117cf2ceadce52d6efbe58a5f3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18586 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-18arm: Add an object file loader for linux and freebsd.Gabe Black
Change-Id: Ie5fd187a4897aa608ffc12278b23d3ee8c0f323c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18585 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-18alpha: Add an object file loader for linux.Gabe Black
Change-Id: I91c4019567bdf74b2517fda597121a6ad107cb86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18584 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-18arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.Gabe Black
This code will be preserved through version control, but otherwise creates clutter and will rot in place since it's never compiled. Change-Id: Id265f6deac445116843956ea5cf1210d8127274e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-17arch-arm: implement VMINNM and VMAXNM scalar versionCiro Santilli
ARMv8.2 16-bit versions have not yet been implemented, but a placeholders were created for them. Refactor the nearby decoding tree to closely match the ARM spec A32 decode table. That piece of the tree can also be called from thumb which decodes it in the same way, although the thumb decode table has a different terminology The old code didn't match neither A32 or T32 terminologies, so it is better to at least match one of them to help verify correctness. Change-Id: Iabbbca2932557cf6c98ce36690c385c3ddf39ed8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18690 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-17arch-arm: implement VMINNM and VMAXNM SIMD versionCiro Santilli
This instruction is backported from aarch64. In order to use the existing fplibMinNum backend, we first move VMIN and VPMIN to use fplib. Adding VMINNM is then trivial. Change-Id: I404daabeb6079f60e51a648a06d5b3e54f1c24a9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18689 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-17arch-arm: rename operands to match spec in isa/formats/fp.isaCiro Santilli
Matches ARM DDI 0487D.a decoding tables. Change-Id: I48338ef956a04308d55d1022229ebe0962a8fe5d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18688 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-14arch-arm: Do not check MustBeOne flag for TLB requests from the prefetcherJavier Bueno
Allow TLB requests generated from prefetchers to override the MustBeOne arch flag. This allows the prefetchers to issue requests without having to know architecutre-specific flags. Change-Id: Id83e0c93f3d1a614da11c4f344ab4dc594423672 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18768 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-11arch-arm: Add initial support for SVE contiguous loads/storesGiacomo Gabrielli
Thanks to Pau Cabre and Adria Armejach Sanosa for their contribution of bugfixes. Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13519 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-05-07x86: Mark translation as delayed in case of a hw page table walkGabor Dozsa
This information is used by the LSQ in the O3 cpu (since commit "51becd2... cpu-o3: O3 LSQ Generalisation") Change-Id: I35fe7e2f8428641d863af0e79e28b0b259fb0b00 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18508 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-04arch-riscv: Implement MHARTID CSRAlec Roelke
This patch implements the MHARTID CSR by intercepting attempts to access it, similar to the way accesses to the performance counters are intercepted, to return the thread's context ID. Change-Id: Ie14a31036fbe0e49fb3347ac0c3c508d9427a10d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16988 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-03sim-se: add eventfd system callBrandon Potter
Change-Id: I7aeb4fe808d0c8f2fb8041e3662d330d8458f09c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12125 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-01 15:55:46 +0000