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2019-05-11arch-arm: Add initial support for SVE contiguous loads/storesGiacomo Gabrielli
Thanks to Pau Cabre and Adria Armejach Sanosa for their contribution of bugfixes. Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13519 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-05-07x86: Mark translation as delayed in case of a hw page table walkGabor Dozsa
This information is used by the LSQ in the O3 cpu (since commit "51becd2... cpu-o3: O3 LSQ Generalisation") Change-Id: I35fe7e2f8428641d863af0e79e28b0b259fb0b00 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18508 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-04arch-riscv: Implement MHARTID CSRAlec Roelke
This patch implements the MHARTID CSR by intercepting attempts to access it, similar to the way accesses to the performance counters are intercepted, to return the thread's context ID. Change-Id: Ie14a31036fbe0e49fb3347ac0c3c508d9427a10d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16988 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-03sim-se: add eventfd system callBrandon Potter
Change-Id: I7aeb4fe808d0c8f2fb8041e3662d330d8458f09c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12125 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-05-03arch-riscv,isa: Fix for compressed jump (c_j) immAvishai Tvila
c_j(al) has a special format, called CJ. The jump offset format is instbits[12:2] --> offset[11|4|9:8|10|6|7|3:1|5] Currently in decoder.isa, c_j format is JOp, the imm and branchTarget are incorrect In the execute section (decoder.isa:228), the imm fields is ignored and the offset is calculated correctlly. As a result, we get decoder flush for each c_j instance I've added CJOp format in compressed.isa, and use it in execute section. In addition, c_j is mappped to jal zero, cj_imm, and actually is neither indirect control nor a function call I fixed the flags accordently. I'll fix all IsRet, IsCall and IsIndirectControl flags for rest of (c_)jal(r) in my next commit. I ran coremark -O0 before my fix and I got 37.7% branch miss-rate, after the fix the branch miss-rate is <13% Change-Id: I608d5894a78a1ebefe36f21e21aaea68b42bccfc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17808 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
2019-04-30arch: Stop using TheISA within the ISAs.Gabe Black
We know for sure what the ISA is, so there's no need for the indirection. Change-Id: I73ff04c50890d40a4c7f40caeee746b68b846cb3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18488 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30x86: Get rid of some unnecessary TheISA-es in x86.Gabe Black
The X86ISA namespace is already available. Change-Id: I5774968fdfb30b01eba52cdec5e6ef2c75cb66e4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18471 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30sparc: Move translation constants from isa_traits.hh into tlb.hh.Gabe Black
These aren't used outside of SPARC. Also get rid of some unused constants. Change-Id: Icfe119f88189348245a6f225a61e62dfa93ea951 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18470 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.Gabe Black
Those types aren't generic or used outside of SPARC. Change-Id: I9bb154920a9625f12388c3d295dc933ab51fadde Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18469 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30arch: Remove the mt.hh switching header.Gabe Black
This header was only useful in MIPS and is only used internally within MIPS. It doesn't need to be a switching header file. Change-Id: Id7005f73b95e122f9ab83b3b657cae3391682f26 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18468 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30cpu: alpha: Delete all occurrances of the simPalCheck function.Gabe Black
This is now handled within the ISA description. Change-Id: Ie409bb46d102e59d4eb41408d9196fe235626d32 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18434 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30alpha: Implement simPalCheck within the ISA description.Gabe Black
This doesn't need to be plumbed through generic interfaces. If the function/instruction got more complex in the future (unlikely since Alpha doesn't really see development these days), it could be moved to a helper function defined within Alpha files. Change-Id: Ib746fad7bb13c5cc9c6ee555c3a46ce686771c12 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18433 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-30cpu: Remove hwrei from the generic interfaces.Gabe Black
This mechanism is specific to Alpha and doesn't belong sprinkled around the CPU's generic mechanisms. Change-Id: I87904d1a08df2b03eb770205e2c4b94db25201a1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18432 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30arch: cpu: Track kernel stats using the base ISA agnostic type.Gabe Black
Then cast to the ISA specific type when necessary. This removes (mostly) an ISA specific aspect to some of the interfaces. The ISA specific version of the kernel stats still needs to be constructed and stored in a few places which means that kernel_stats.hh still needs to be a switching arch header, for instance. In the future, I'd like to make the kernel its own object like the Process objects in SE mode, and then it would be able to instantiate and maintain its own stats. Change-Id: I8309d49019124f6bea1482aaea5b5b34e8c97433 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18429 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-30alpha: Implement HWREI in the ISA.Gabe Black
This moves it out of generic interfaces and the CPU implementations. Change-Id: I6767d6b26d0ae128b5bdad5830dce838be74e256 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18431 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-30alpha: Add some control registers to the ISA operands list.Gabe Black
These will be used in the in-ISA HWREI implementation. Change-Id: Ia9f7bf1aa2dbd764c878911c2cba680840397c62 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18430 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-29mips: Implement readRegOtherThread and setRegOtherThread directly.Gabe Black
These accessors can be implemented as helper functions within MIPS without having to plumb them through a bunch of common interfaces. There are a few problems with the way they were implemented which are carried forward to this new implementation as well. That includes hiding the register accesses from the ISA parser and therefore the CPU's dependency tracking, potentially panicing or accessing a non existent thread based on a possible set of input values, and modifying register values even if an instruction is being executed speculatively. Fixing these problems would be fairly involved and require changing how dependencies are tracked in all the CPUs so that they can act across threads, and also how registers are handled in the ISA description itself. The original implementation just punted on making this work in CPUs other than the minor CPU (and potentially one or more CPU models that were not and/or are not in the code base). Where as that implementation might have paniced if these methods were called, this will attempt to work, but may have incorrect behavior based on the limitations described above. I'd consider this an acceptable tradeoff, at least for the time being. Change-Id: I94adceafb9812a8641c76ea3518c3285c31baf51 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18435 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-29arch-arm: Faults DebugFlag now printing inst opcode if availableGiacomo Travaglini
This makes it easier to debug unimplemented instructions. Change-Id: Iaaa288037326722f07251299fd68eacb2e295376 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18396 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-29arch-arm: Report real instruction encoding when UndefinedGiacomo Travaglini
When dumping the opcode that caused an Undefined Instruction, we just want to dump the real instruction encoding, and not the extended version with metabits (like thumb, bigThumb etc). This was not appening when panicking in SE mode. The patch is also replacing custom masking in the Unknown(64) disassembler in favour of ArmStaticInstruction::encoding() helper. Change-Id: I9eb6fd145d02b4b07bb51f0bd89ca014d6d5a6de Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18395 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
The AuxVector type has a bunch of accessors which just give access to the underlying variables through references. We might as well just make those members accessible directly. Also, the AuxVector doesn't need to handle endianness flips itself. We can tell the byteswap mechanism how to flip an AuxVector, and let it handle that for us. This gets rid of the entire .cc file which was complicated by trying to both hide the ISA specific endianness translations, and instantiate templated functions in a .cc. Change-Id: I433cd61e73e0b067b6d628fba31be4a4ec1c4cf0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18373 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-28mem: Remove the ISA specialized versions of port proxy's read/write.Gabe Black
These selected their behavior based on ifdefs and had to be disabled when on the NULL ISA. The versions which take an explicit endianness have been renamed to just read/write instead of readGtoH and writeHtoG since the direction of the translation is obvious from context. Change-Id: I6cfbfda6c4481962d442d3370534e50532d41814 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18372 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-28mem: Minimize the use of MemObject.Gabe Black
MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed. Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-04-26arch-arm: updateMiscReg not setting isHyp in aarch64Giacomo Travaglini
The isHyp flag should be set for a TLB::NormalTran when in EL2. This was happening in aarch32 only, where the CPSR mode is checked, while aarch64 was only using it for explicit EL2 translations, like for AT instructions. Change-Id: I54605811e9dde75b5cf8868190b0f4c2a8d46570 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18394 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-26arm: Factor some repetition out of the ProcessInfo constructor.Gabe Black
Change-Id: I34f952d1097886704d37304478de125a915b2615 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18371 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-25arm: Fix some style issues in stacktrace.cc.Gabe Black
De-indent the ArmISA namespace, and wrap some overly long lines. Change-Id: Idc02b025bdfda483ddbd27d662e2314a5cbcb23c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18370 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-25x86: Refactor the ProcessInfo constructor.Gabe Black
That function had a lot of repetition which is easily factored out into its own function. Change-Id: I3b7a522de2ba808856bb59df75b80efde6780e3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18369 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-25x86: Fix some style issues in stacktrace.cc.Gabe Black
De-indent the X86ISA namespace, and wrap some overly long lines. Change-Id: I01a6b66a1cf721e16e4ed4dd1c3469ee112e9177 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18368 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25arch-arm: Remove un-needed hyp flag in TLBI operationsGiacomo Travaglini
The hyp flag was probably a legacy pre-v8 flag distinguishing invalidation targeting PL2 translation regime (hyp mode). Since the introduction of target_el parameter, hyp boolean is not needed anymore. The patch works by setting the hyp flag in the flush* methods in the TLB automatically by checking if target_el == EL2. Change-Id: I798009e09ff24a383dea871e348188bae2685e8e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18389 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-25arch-arm: Correct target EL field in TLBI operationsGiacomo Travaglini
Some TLB Invalidation operations affecting the EL2 translation regime were marked as targeting EL1 instead of EL2 Change-Id: I77821eec7a409e9df6a6814855f9a375832ffe74 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18388 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-22sim-se: Enhance clone for X86KvmCPUAlexandru Dutu
This changeset enables clone to work with X86KvmCPU model, which will allow running multi-threaded applications at near hardware speeds. Even though the application is multi-threaded, the KvmCPU model uses one event queue, therefore, only one hardware thread will be used, through KVM, to simulate multiple application threads. Change-Id: I2b2a7b1edb1c56eeb9c4fa0553cd236029cd53f8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18268 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-22cpu: Eliminate the ProxyThreadContext class.Gabe Black
Replace it with direct inheritance from the ThreadContext class in the SimpleThread class which was the only place it was used. Also take the opportunity to use some specialized types instead of ints, etc., add some consts, and fix some style issues. Change-Id: I5d2cfa87b20dc43615e33e6755c9d016564e9c0e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18048 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-11arch-arm: Enable PMSELR_EL0 read in PMUGiacomo Travaglini
Change-Id: Ic1ec1d03464a7ce42295cee8a9f4ebcd3e90def1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17948 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-03misc: Removed inconsistency in O3* debug msgsAndrea Mondelli
Added consistency in the DEBUG message form, to allow a better parsing. Fixed sn/tid type parameter. Removed some annoying newlines Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17248 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-04-02dev-arm: Make GICv3 maintenance interrupt an ArmInterruptGiacomo Travaglini
Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-04-01dev-arm: Correct cast of template parameterAndrea Mondelli
Clang with -Wconstant-conversion is _very_ restrictive on casting. The shift operator results in an incorrect promotion. This patch add a compile-time static cast that remove the error when clang is used. Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17308 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-28arch-arm: Fix use of bitwise operators on booleansJavier Setoain
Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17288 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-28arch-arm: Fix index generation for VecElem operandsGiacomo Travaglini
Current operand generation is not providing VecElems with the right vector index and element index. The bug was covered when registers were 128 bit wide, but with SVE we have augmented the vector register size and the bug has been exposed. E.g. With dest = 2, FpDestP2 = (vec_index = 0, elem_index = 4) whereas it should be FpDestP2 = (vec_index = 1, elem_index = 0) Change-Id: Iad02fb477afd0d3dd3d437bf2ca4338fbd142107 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17710
2019-03-25arch-arm: Add missing fall-through defaultsJavier Setoain
Change-Id: Ie64b83d754c4719a77c7788879be71304a9b786e Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17289 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-03-25arch-power: Rename program counter registersSandipan Das
The Power ISA specification lists the Program Counter (PC) and the Next Program Counter (NPC) registers as Current Instruction Address (CIA) and Next Instruction Address (NIA). This applies the ISA naming convention for these two registers. Change-Id: I8b9094ab1c809f4dfdb4d7330c17f360adf063e9 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16603 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-25arch-power: Simplify doubleword operand typesSandipan Das
Currently, 'sq' and 'uq' are used to represent signed and unsigned doublewords respectively. Since all recent Power ISA specifications list 128-bit quadwords as a valid data type, it may be misleading to use the current terminology in case support for such operands are added in the future. So, to simplify this, 'sd' and 'ud' are used to represent signed and unsigned doublewords respectively. Change-Id: Ie7831c596fc8f9ddfdf3b652c37cfe26484ebe01 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16602 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-22sim-se: Fixed initialization array sizeTiago Muck
Doubled the size of the zeroed auxiliary vector since 2 * intSize on aarch64 > sizeof(uint64). Change-Id: I5196b000a696e9ea3f2b5daa5d5bb071794369aa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17088 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-03-21dev-arm: ambiguous use of getPort()Andrea Mondelli
The recent introduction of getPort() creates a conflict with the existing method used in arm MMU. This patch rename the old getPort() in getDMAPort() according to the returned value (DmaPort class type) Change-Id: Ief3d83650fd6b08490522341631244be06e380ce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17469 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
Replace the getMasterPort, getSlavePort, and getEthPort functions with getPort, and remove extraneous mechanisms that are no longer necessary. Change-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-14arch-arm,cpu: Add initial support for Arm SVEGiacomo Gabrielli
This changeset adds initial support for the Arm Scalable Vector Extension (SVE) by implementing: - support for most data-processing instructions (no loads/stores yet); - basic system-level support. Additional authors: - Javier Setoain <javier.setoain@arm.com> - Gabor Dozsa <gabor.dozsa@arm.com> - Giacomo Travaglini <giacomo.travaglini@arm.com> Thanks to Pau Cabre for his contribution of bugfixes. Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-11arch-hsail: changed gen.py shebang from python(3) to python2.7Ryan Gambord
gen.py includes code_formatter from m5.util. code_formatter uses the python2 __metaclass__ attribute, which is ignored by python3, causing the code_formatter.pattern attribute to be unset. This prevented scons from building against HSAIL_X86 Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu> Change-Id: I5a8bf9e730fd629eb7f9a7ac2dce928235a0dae4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17008 Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-03-11arch-arm: Fixing implicit fallthrough build errorsRyan Gambord
2c242d6 introduced implicit-fallthrough errors when building against ARM. Added "default: return new Unknown(machInst);" to offending switch statements; please verify this is the corret behavior Signed-off-by: Ryan Gambord Change-Id: I5f5e3661ec562d4a3b2699e07d1195e6877ff959 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17071 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-03-01mem-cache: alias to mem::getMasterPort in TLB classAndrea Mondelli
TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and hides the BaseTLB::getMasterPort(). The TLB::getMasterPort() is renamed according to the expected behavior. Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8 Reviewed-on: https://gem5-review.googlesource.com/c/16648 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-01arch-arm: implement floating point aarch32 VCVTA familyCiro Santilli
These instructions round floating point to integer, and were added to aarch32 as an extension to ARMv7. Change-Id: I62d1705badc95a4e8954a5ad62b2b6bc9e4ffe00 Reviewed-on: https://gem5-review.googlesource.com/c/16788 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-23python: Enforce absolute imports for Python 3 compatibilityAndreas Sandberg
Change-Id: Ia88d7fd472f7aed9b97df81468211384981bf6c6 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15983 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-20x86: Call the base class's regStats in X86ISA::TLBBagus Hanindhito
When I try to build x86 architecture and run the se.py sample script with helloworld example, there is a panic warning stated "Not all stats have been initialized. You may need to add <ParentClass>::regStats() to a new SimObject's regStats() function." I see that in x86 tlb.cc, there is no initialization in regStats() function that causes memory allocation error in some machine which make gem5 exit abnormally. I add the BaseTLB::regStats(); on TLB::regStats() method and can solve the problem Change-Id: I8b62bebc15f896c3136ff4f8253dabbf998f618f Reviewed-on: https://gem5-review.googlesource.com/c/16522 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
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