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2019-02-18arch-generic: Making base TLB class a MemObjectIvan Pizarro
Allow configuring a TLB hierarchy using ports Change-Id: I1f791829d4e072a9104e67eacf69a69de9543634 Reviewed-on: https://gem5-review.googlesource.com/c/14117 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-18arch-arm: Move GICv3 detection at startup timeGiacomo Travaglini
At the moment the haveGicV3 parameter is used only to signal its presence when reading the MISCREG_ID_AA64PFR0_EL1 register. It depends on the system->getGIC pointing to a GICv3 model. However this pointer is set in the System only at init time (after construction), which means that the haveGICv3CPUInterface will always be false. This patch is fixing this by moving the parameter initialization at startup time, together with the cpu interface registration. Change-Id: I8da6711ea741ecd0f78ec8ca60a8c3ae3bca2421 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16483 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-13sim-se: update the arm kernel versionAyaz Akram
This change is needed to run cpu tests with ARM binaries compiled with newer linux kernel headers Change-Id: I6cbf132c38d4b18f971ee32272ddb6a5a791a625 Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15855 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-12python: Replace dict.has_key with 'key in dict'Andreas Sandberg
Python 3 has removed dict.has_key in favour of 'key in dict'. Change-Id: I9852a5f57d672bea815308eb647a0ce45624fad5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15987 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files. Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-12arch-mips: Remove unused Python fileAndreas Sandberg
Change-Id: I7155915fccdec1d9f116f2a8617474188a91165b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16302 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-08riscv: fix AMO, LR and SC instructionsTuan Ta
(1) Atomic Memory Operation (AMO) This patch changes how RISC-V AMO instructions are implemented. For each AMO, instead of issuing a locking load and an unlocking store request to downstream memory system, this patch issues a single memory request that contains a corresponding AtomicOpFunctor to the memory system. Once the memory system receives the request, the atomic operation is executed in one single step. This patch also changes how AMO instructions handle acquire and release flags in AMOs (e.g., amoadd.aq and amoadd.rl). If an AMO is associated with an acquire flag, a memory fence is inserted after the AMO completes as a micro-op. If an AMO is associated with a release flag, another memory fence is inserted before the AMO executes. If both flags are specified, the AMO is broken down into a sequence of 3 micro-ops: mem fence -> atomic RMW -> mem fence. This change makes this AMO implementation comply to the release consistency model. (2) Load-Reserved (LR) and Store-Conditional (SC) Addresses locked by LR instructions are tracked in a stack data structure. LR instruction pushes its target address to the stack, and SC instruction pops the top address from the stack. As specified by RISC-V ISA, a SC fails if its target address does not match with the most recent LR. Previously, there was a single stack for all hardware thread contexts. A shared stack between thread contexts can lead to a infinite sequence of failed SCs if LRs from other threads keep pushing new addresses to this stack. This patch gives each context its private stack to address the problem. This patch also adds extra memory fence micro-ops to lr/sc to guarantee a correct execution order of memory instructions with respect to release consistency model. Change-Id: I1e95900367c89dd866ba872a5203f63359ac51ae Reviewed-on: https://gem5-review.googlesource.com/c/8189 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2019-02-08riscv: fixed syscall return valueTuan Ta
In case of failure, a syscall returns a negative value encoding the error code. This patch makes the risc-v implementation returns the encoded value instead of its absolute value upon a failure of a syscall. Change-Id: I6032b0337fe1cff5b326dbc6bb3b87a415f03300 Reviewed-on: https://gem5-review.googlesource.com/c/9627 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2019-02-08riscv: ignore nanosleep syscallTuan Ta
Change-Id: I564a09564da668a5db3e75f15b33efaca363d71a Reviewed-on: https://gem5-review.googlesource.com/c/9624 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-08arch-riscv: initialize RISC-V's thread pointer register in clone syscallTuan Ta
This patch initializes thread pointer register to Thread Local Storage (TLS)'s pointer given to a clone system call. Change-Id: I03e2cf4763e6a0ed31f357772a513a05e1e3461b Reviewed-on: https://gem5-review.googlesource.com/c/9622 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2019-02-08arch-arm: Fix Virtual interrupts in AArch64Giacomo Travaglini
Checking if cpsr.mode is equal to MODE_HYP doesn't work for AArch64. This is because AArch64 is using different modes when in EL2, like EL2T and EL2H. This made Virtual Interrupts to be triggered even when executing in EL2 (hypervisor) whereas they should interrupt the scheduled VM only (Non-Secure EL0 and EL1). This patch is fixing this by using the generic currEL() helper for getting the exception level, which is working for both AArch32 and AArch64. Change-Id: I08640050ef06261f280ba1e63ca9f32c805af845 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16202 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-08arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30Giacomo Travaglini
Change-Id: I649f8507ccb6c814b46b0b9b7e39dc912ecd9006 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16242
2019-02-08arch-arm: Allow ArmPPI usage for PMUGiacomo Travaglini
Differently from ArmSPIs, ArmPPI interrupts need to be instantiated by giving a ThreadContext pointer in the ArmPPIGen::get() method. Since the PMU is registering the ThreadContext only at ISA startup time, ArmPPI generation in deferred until the PMU has a non NULL pointer. Change-Id: I17daa6f0e355363b8778d707b440cab9f75aaea2 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16204 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-08arch-arm: Fix initialization of PMU countersRuben Ayrapetyan
A version of Linux kernel initializes counters before enabling them. Without this change, gem5 overwrites the value of counter, which causes incorrect counter values derived by kernel. Change-Id: If0c515111103018d5f65f74434d7711a67aeaee4 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16203 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-02-07arch-riscv: Enable support for riscv 32-bit in SE mode.Austin Harris
This patch splits up the riscv SE mode support for 32 and 64-bit. A future patch will add support for decoding rv32 instructions. Change-Id: Ia79ae19f753caf94dc7e5830a6630efb94b419d7 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/15355 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2019-02-06riscv: remove NonSpeculative flag from fence instTuan Ta
Fence instruction origially had two flags NonSpeculative and MemBarrier. In O3 model, MemBarrier instructions are inserted into the instruction queue by the InstructionQueue::insertBarrier (at src/cpu/o3/iew_impl.hh:1083). Barrier instructions are implicitly assumed to be non-speculative. Adding NonSpeculative flag to fence instruction makes it inserted into the instruction queue twice (at src/cpu/o3/iew_impl.hh:1083 and :1111). This can lead to a deadlock if both pointers to the instruction are not cleared from the queue when the instruction retires. This patch removes NonSpeculative flag from the fence inst. Change-Id: I26573d12a0b52f43b73c0e51158286dc98d05ea4 Reviewed-on: https://gem5-review.googlesource.com/c/8183 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2019-02-06arch-riscv: Initialize interrupt maskTuan Ta
This patch initializes RISCV interrupt mask to 0. Change-Id: I56289d9f3f319e239e305befea006a0ad4d86b75 Reviewed-on: https://gem5-review.googlesource.com/c/16162 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-05misc: added missing override specifierAndrea Mondelli
Added missing specifier for various virtual functions. Change-Id: I4783e92d78789a9ae182fad79aadceafb00b2458 Reviewed-on: https://gem5-review.googlesource.com/c/16103 Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-02-05riscv: Get rid of ISA specific register types in Interrupts.Austin Harris
Change-Id: I5542649c6af27a286f276a289b86c40dd7e32abc Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/c/16122 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
Most architectures weren't using the CCReg type, and in x86 and arm it was already a uint64_t. Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6 Reviewed-on: https://gem5-review.googlesource.com/c/14515 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31power: Get rid of some ISA specific register types.Gabe Black
Change-Id: If63acb10705a9f442255680917d16630748ca8e1 Reviewed-on: https://gem5-review.googlesource.com/c/14465 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31null: Get rid of some register type definitions.Gabe Black
These are no longer used. Change-Id: Ic6a35e8a7e25eab9d21a3eef683914e01508c6d7 Reviewed-on: https://gem5-review.googlesource.com/c/14463 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31mips: Stop using architecture specific register types.Gabe Black
Change-Id: I764f6eea214ba4e03cc0fe19a21abcb0ebd04408 Reviewed-on: https://gem5-review.googlesource.com/c/14462 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31alpha: Stop using architecture specific register types.Gabe Black
Change-Id: I4052000014c9f6f9ecefd3f37e58595c61599484 Reviewed-on: https://gem5-review.googlesource.com/c/14461 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31x86: Stop using/defining some ISA specific register types.Gabe Black
These have been replaced with the generic RegVal type. Change-Id: I75c1134212067dea43aa0903d813633e06f3d6c6 Reviewed-on: https://gem5-review.googlesource.com/c/14476 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31riscv: Get rid of some ISA specific register types.Gabe Black
Change-Id: Ie812cf1d42536094273ba2ec731c16cca38db100 Reviewed-on: https://gem5-review.googlesource.com/c/14466 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
Now that there's no plain FloatReg, there's no reason to distinguish FloatRegBits with a special suffix since it's the only way to read or write FP registers. Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded Reviewed-on: https://gem5-review.googlesource.com/c/14460 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector Extension (SVE), introduce the notion of a predicate register file. This changeset adds this feature across architectures and CPU models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13715 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-30arch-arm, configs: Create single instance of DTB autogenerationGiacomo Travaglini
This patch is rewriting the DTB autogeneration functions available in fs_bigLITTLE.py and fs.py as a single method in the GenericArmSystem so that other configuration scripts can make use of it. Change-Id: I492bbf77e6b0ac5c5fbdbc75c0eecba29bd63bda Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15958 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch-arm: Remove floatReg operand typeGiacomo Travaglini
Change-Id: I87553257ce9c42d0e2514d5a1f010bc6e2e7f21e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15604 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch-arm: Use VecElem instead of FloatReg for FP instructionGiacomo Travaglini
SIMD & FP Operations use FloatRegs in AArch32 mode and VecRegs in AArch64 mode. The usage of two different register pools breaks interprocessing between A32 and A64. This patch is changing definition of arm operands so that they are backed by VecElems in A32, which are mapped to the same storage as A64 VecRegs. Change-Id: I54e2ea0ef1ae61d29aca57ab09acb589d82c1217 Reviewed-on: https://gem5-review.googlesource.com/c/15603 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch: Fix VecElem Operand generation in ISA parserGiacomo Travaglini
Fixes include: * Change of reg_class: VecElemClass in lieau of non-existing VectorElemClass. * Removal of unused regId in operand constructor * makeRead and makeWrite are using VecElem (which is a typedef of uint32_t) as a source/destination type, regardless of the real operand type (which is specified by ctype) Change-Id: I4588e1120e1fc8fdb68b2b2f05d5e3692c55b2e8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15602 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-25cpu, arch, arch-arm: Wire unused VecElem code in the O3 modelGiacomo Travaglini
VecElem code had been introduced in order to simulate change of renaming for vector registers. Most of the work is happening on the rename_map switchRenameMode. Change of renaming can happen after a squash in the pipeline. This patch is also changing the interface to the ISA part so that a PCState is used instead of ISA in order to check if rename mode has changed. Change-Id: I8af795d771b958e0a0d459abfeceff5f16b4b5d4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15601
2019-01-25arch-arm: Inital vector rename mode depending on A32/A64Giacomo Travaglini
Change-Id: I6b99833641b0ab6534471d5ff3ca5d3791285481 Reviewed-on: https://gem5-review.googlesource.com/c/15599 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch-arm: Remove unused float operandsGiacomo Travaglini
Removing FaP1 and FDest2 since they are not currently used by any ARM instruction. Change-Id: I4251dfcdd3f4434caaf0bdab507c1c3bd53fb5d2 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15596 Reviewed-by: Ciro Santilli <ciro.santilli@gmail.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-25arch: Provide traceback when parsing ISA codeGiacomo Travaglini
There is no line information When the ISA code is executed inside the isa_parser environment and an error is encountered. The build stops and reports the line of the let block containing the error. This patch is enhacing the error reporting by printing the traceback of the faulting ISA code. Change-Id: I3acd17f0d78b2feb8fe6e48808a094c5b81624e6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15595 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-24hsail: Remove the MiscReg type.Gabe Black
It has been replaced by the ISA agnostic RegVal. Change-Id: I563ea3852e37b5c1cf51eb0ac9a6f2a827ba89cf Reviewed-on: https://gem5-review.googlesource.com/c/14464 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-24base: arch: Get rid of the now unused FloatRegVal type.Gabe Black
This type is no longer used since FP registers are accessed as integer bit patterns. Change-Id: I1070f9443d6247165fd64c6bc041811c28287e9f Reviewed-on: https://gem5-review.googlesource.com/c/14459 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-23arch-arm: Implement LoadAcquire/StoreRelease in AArch32Giacomo Travaglini
This patch is implementing LoadAcquire/StoreRelease instructions in AArch32, which were added in ARMv8-A only and where not present in ARMv7. Change-Id: I5e26459971d0b183a955cd7b0c9c7eaffef453be Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15817 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-23arch-arm: IsStoreConditional flag set depending on flavorGiacomo Travaglini
This patch is aligning A32 with A64 where the IsStoreConditional flag doesn't have to be specified manually in the instruction implementation, but will be automatically added to any exclusive store. Change-Id: Id02ed6fc2beeca6d125017393714a7c6eb3d8a33 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15816 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-23arch-arm: Remove SWP and SWPB instructionsGiacomo Travaglini
The SWP and SWPB instructions have been removed from AArch32. It was previously (ARMv7) possible to enable them with the ID_ISAR0.Swap bits, which are now hardcoded to 0b0000 (SWP and SWPB not implemented) Change-Id: Ic32b534454a7e0f7494a6f0b5e11182c65b3fe24 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15815 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-23arm: Replace MiscReg with RegVal in utility.(hh|cc).Gabe Black
These uses snuck in after the previous pass which made this switch in the rest of these files. Change-Id: Ie891c6ec393a65f1c57c54301f0a2bb920d38bb0 Reviewed-on: https://gem5-review.googlesource.com/c/15795 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-22sparc: Get rid of some register type definitions.Gabe Black
These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44 Reviewed-on: https://gem5-review.googlesource.com/c/13627 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-22arch: cpu: Stop passing around misc registers by reference.Gabe Black
These values are all basic integers (specifically uint64_t now), and so passing them by const & is actually less efficient since there's a extra level of indirection and an extra value, and the same sized value (a 64 bit pointer vs. a 64 bit int) is being passed around. Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3 Reviewed-on: https://gem5-review.googlesource.com/c/13626 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-22arm: Get rid of some register type definitions.Gabe Black
These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: Ief1cd85d0eff7156282ddb1ce168a2a5677f7435 Reviewed-on: https://gem5-review.googlesource.com/c/13625 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-01-22arch-arm: implement the GDB XML target description for ARMCiro Santilli
The supported registers are essentially the same as before this patch, but it is now trivial to make new registers visible in future commits. Change-Id: Id15b7aeccca824c342e49a626d2877179474f3d4 Reviewed-on: https://gem5-review.googlesource.com/c/15138 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-22arch-arm: Move AArch32 IMPLEMENTATION DEFINED registersGiacomo Travaglini
Moving AArch32 instruction accessing IMPLEMENTATION DEFINED registers from pseudo.[cc/hh] to misc.[cc/hh] in order to symmetrically match with AArch64 implementation. Change-Id: I27b0d65925d7965589b765269ae54129426e4c88 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15735 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-01-22sim-se add readv and modifies writevBrandon Potter
Change-Id: I6cbce4389d5697da34058dc910306394e48c6582 Reviewed-on: https://gem5-review.googlesource.com/c/12117 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add ability to get/set sock metadataBrandon Potter
Add getsockopt, getsockname, setsockname, and getpeername system calls. Change-Id: Ifa1d9a95f15b4fb12859dbfd3c4bd248de2e3d32 Reviewed-on: https://gem5-review.googlesource.com/c/12116 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-22sim-se: add syscalls related to pollingBrandon Potter
Fix poll so that it will use the syscall retry capability instead of causing a blocking call. Add the accept and wait4 system calls. Add polling to read to remove deadlocks that occur in the event queue that are caused by blocking system calls. Modify the write system call to return an error number in case of error. Change-Id: I0b4091a2e41e4187ebf69d63e0088f988f37d5da Reviewed-on: https://gem5-review.googlesource.com/c/12115 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
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