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AgeCommit message (Collapse)Author
2011-02-11VNC: Add VNC server to M5Ali Saidi
2011-02-02Time: Add serialization functions to the Time class.Gabe Black
2011-01-22refcnt: Change things around so that we handle constness correctly.Nathan Binkert
To use a non const pointer: typedef RefCountingPtr<Foo> FooPtr; To use a const pointer: typedef RefCountingPtr<const Foo> ConstFooPtr;
2011-01-19Time: Add setTick and getTick functions to the Time class.Gabe Black
2011-01-15time: improve time datastructureNathan Binkert
Use posix clock functions (and librt) if it is available. Inline a bunch of functions and implement more operators. * * * time: more cleanup
2011-01-10stats: Add a histogram statistic typeNathan Binkert
2011-01-10stats: fix the distribution statNathan Binkert
2011-01-10Curtick: Fix mysql.cc build needing curTick.Gabe Black
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values.
2011-01-04Params: Print the IP components in the right order.Gabe Black
2011-01-03Move sched_list.hh and timebuf.hh from src/base to src/cpu.Steve Reinhardt
These files really aren't general enough to belong in src/base. This patch doesn't reorder include lines, leaving them unsorted in many cases, but Nate's magic script will fix that up shortly. --HG-- rename : src/base/sched_list.hh => src/cpu/sched_list.hh rename : src/base/timebuf.hh => src/cpu/timebuf.hh
2011-01-03Delete unused files from src/base directory.Steve Reinhardt
2011-01-03Make commenting on close namespace brackets consistent.Steve Reinhardt
Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript.
2011-01-03RefCount: Fix reference counting pointer == and != with a T* on the left.Gabe Black
These operators were expecting a const T& instead of a const T*, and were not being picked up and used by gcc in the right places as a result. Apparently no one used these operators before. A unit test which exposed these problems, verified the solution, and checks other basic functionality is on the way.
2010-12-21Get rid of unused file src/base/dbl_list.hhSteve Reinhardt
2010-11-23Copyright: Add AMD copyright to the param changes I just made.Gabe Black
2010-11-23Params: Add parameter types for IP addresses in various forms.Gabe Black
New parameter forms are: IP address in the format "a.b.c.d" where a-d are from decimal 0 to 255. IP address with netmask which is an IP followed by "/n" where n is a netmask length in bits from decimal 0 to 32 or by "/e.f.g.h" where e-h are from decimal 0 to 255 and which is all 1 bits followed by all 0 bits when represented in binary. These can also be specified as an integral IP and netmask passed in separately. IP address with port which is an IP followed by ":p" where p is a port index from decimal 0 to 65535. These can also be specified as an integral IP and port value passed in separately.
2010-11-20random: small comment about our random number generator and its originNathan Binkert
2010-11-19SCons: Support building without an ISAAli Saidi
2010-11-08sim: Use forward declarations for ports.Ali Saidi
Virtual ports need TLB data which means anything touching a file in the arch directory rebuilds any file that includes system.hh which in everything.
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense.
2010-09-10style: fix sorting of includes and whitespace in some filesNathan Binkert
2010-08-23Loader: Don't insert symbols into the symbol table that begin wiht '$'.Ali Saidi
2010-08-23ARM: Add I/O devices for booting linuxAli Saidi
--HG-- rename : src/dev/arm/Versatile.py => src/dev/arm/RealView.py rename : src/dev/arm/versatile.cc => src/dev/arm/realview.cc rename : src/dev/arm/versatile.hh => src/dev/arm/realview.hh
2010-08-23Loader: Use address mask provided to load*Symbols when loading the symbols ↵Ali Saidi
from the symbol table.
2010-08-23BASE: Fix genrand to generate both 0s and 1s when max equals one.Ali Saidi
previously was only generating 0s.
2010-08-23stats: Fix off-by-one error in distributions.Ali Saidi
bkt size isn't evenly divisible by max-min and it would round down, it's possible to sample a distribution and have no place to put the sample. When this case occured the simulator would assert.
2010-07-21stats: unify the two stats distribution type betterNathan Binkert
2010-07-21stats: cleanup a few small problems in statsNathan Binkert
2010-07-05checkpointing: another small overload fixSteve Reinhardt
On Nate's advice, overload 'char' as well as 'signed char' and 'unsigned char'.
2010-07-05sim: fold StartupCallback into SimObjectSteve Reinhardt
There used to be a reason to have StartupCallback be a separate object, but not any more. Now it's just confusing.
2010-06-15stats: rename print to display in the mysql code too...sorryNathan Binkert
2010-06-15stats: rename print to display so it work in pythonNathan Binkert
2010-06-15stats: only consider a formula initialized if there is a formulaNathan Binkert
2010-06-14stats: get rid of the never-really-used event stuffNathan Binkert
2010-06-10ruby: get rid of the Map classNathan Binkert
2010-06-10ruby: get rid of Vector and use STLNathan Binkert
add a couple of helper functions to base for deleteing all pointers in a container and outputting containers to a stream
2010-06-03Stats: fix dist stat and enable VectorDistStatLisa Hsu
2010-06-02ARM: Detect thumb mode elf images.Gabe Black
2010-05-06compile: don't #include unnecessary stuffNathan Binkert
Time from base/time.hh has a name clash with Time from Ruby's TypeDefines.hh. Eventually Ruby's Time should go away, so instead of fixing this properly just try to avoid the clash.
2010-04-18callback: Make helper functions that create callback objects for youNathan Binkert
clean up callback stuff a little bit while we're at it.
2010-04-02refcnt: no default copy contructor or copy operatorNathan Binkert
We shouldn't allow these because the default versions will copy the reference count which is definitely not what we want.
2010-02-23stats: this makes some fixes to AverageStat and AverageVector.Lisa Hsu
Also, make Formulas work on AverageVector. First, Stat::Average (and thus Stats::AverageVector) was broken when coming out of a checkpoint and on resets, this fixes that. Formulas also didn't work with AverageVector, but added support for that.
2010-01-23build: need to include cstdioNathan Binkert
2009-11-04build: fix compile problems pointed out by gcc 4.4Nathan Binkert
2009-10-27POWER: Add support for the Power ISATimothy M. Jones
This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06.
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-07-27ARM: Detect OABI binaries and complain that they're no-longer supported.Ali Saidi
2009-07-01ARM: Add a findLsbSet function and use it to implement clz.Gabe Black