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2007-01-16Don't add symbols for loaded files to symbol table since they are pretty ↵Ali Saidi
much meaningless with all the copying that goes on --HG-- extra : convert_revision : 4d2c1bb72c0344d78d9c3d5958feb3de247102a0
2006-12-27No need to use NULL, just use 0Nathan Binkert
The result of operator= cannot be an l-value --HG-- extra : convert_revision : df97a57f466e3498bd5a29638cb9912c7f3e1bd4
2006-12-24remove some output formatting stuff that we don't useNathan Binkert
--HG-- extra : convert_revision : 367917499d3d7aebd0a91dad28c915bc85def624
2006-12-18cast chars to int when we want to print integers so we get a numberNathan Binkert
instead of a character --HG-- extra : convert_revision : 7bfa88ba23ad057b751eb01a80416d9f72cfe81a
2006-12-15Merge zizzer:/bk/sparcfsLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem --HG-- extra : convert_revision : 92a865a90a7c3e251ed1443f79640f761b359c1d
2006-12-12Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)Ali Saidi
Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing) Fix tcc instruction igoner in legion-lock stuff to be correct in all cases Have console interrupts warn rather than panicing until we figure out what to do with interrupts src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: add a magic miscreg which reads all the bits the tlb needs in one go src/arch/sparc/tlb.cc: initialized the context type and id to reasonable values and handle block init stores src/arch/sparc/tlb_map.hh: fix bug in tlb map code src/base/range_map.hh: fix bug in rangemap code and add range_multimap (these are probably useful for bus range stuff) src/cpu/exetrace.cc: fixup tcc ignore code to be correct src/dev/sparc/t1000.cc: make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out src/unittest/rangemaptest.cc: fix up the rangemap unit test to catch the missing case --HG-- extra : convert_revision : 70604a8b5d0553aa0b0bd7649f775a0cfa8267a5
2006-12-06Many more fixes for SPARC_FS. Gets us to the point where SOFTINT startsAli Saidi
getting touched. configs/common/FSConfig.py: Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs src/arch/isa_parser.py: we should readmiscregwitheffect not readmiscreg src/arch/sparc/asi.cc: Fix AsiIsNucleus spelling with respect to header file Add ASI_LSU_CONTROL_REG to AsiSiMmu src/arch/sparc/asi.hh: Fix spelling of two ASIs src/arch/sparc/isa/decoder.isa: switch back to defaults letting the isa_parser insert readMiscRegWithEffect src/arch/sparc/isa/formats/mem/util.isa: Flesh out priviledgedString with hypervisor checks Make load alternate set the flags correctly src/arch/sparc/miscregfile.cc: insert some forgotten break statements src/arch/sparc/miscregfile.hh: Add some comments to make it easier to find which misc register is which number src/arch/sparc/tlb.cc: flesh out the tlb memory mapped registers a lot more src/base/traceflags.py: add an IPR traceflag src/mem/request.hh: Fix a bad assert() in request --HG-- extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
2006-12-04More changes to get SPARC fs closer. Now at 1.2M cycles before differenceAli Saidi
configs/common/FSConfig.py: seperate the hypervisor memory and the guest0 memory. In reality we're going to need a better way to do this at some point. Perhaps auto generating the hv-desc image based on the specified config. src/arch/sparc/isa/decoder.isa: change reads/writes to the [hs]tick(cmpr) registers to use readmiscregwitheffect src/arch/sparc/miscregfile.cc: For niagra stick and tick are aliased to one value (if we end up doing mps we might not want this). Use instruction count from cpu rather than cycles because that is what legion does we can change it back after were done with legion src/base/bitfield.hh: add a new function mbits() that just masks off bits of interest but doesn't shift src/cpu/base.cc: src/cpu/base.hh: add instruction count to cpu src/cpu/exetrace.cc: src/cpu/m5legion_interface.h: compare instruction count between legion and m5 too src/cpu/simple/atomic.cc: change asserts of packet success to if panics wrapped with NDEBUG defines so we can get some more useful information when we have a bad address src/dev/isa_fake.cc: src/dev/isa_fake.hh: src/python/m5/objects/Device.py: expand isa fake a bit more having data for each size request, the ability to have writes update the data and to warn on accesses src/python/m5/objects/System.py: convert some tabs to spaces src/python/m5/objects/T1000.py: add more fake devices for each l1 bank and each memory controller --HG-- extra : convert_revision : 8024ae07b765a04ff6f600e5875b55d8a7d3d276
2006-12-02Make cache compression policy a runtime virtual thingSteve Reinhardt
instead of a template policy. --HG-- extra : convert_revision : 6a4ac7a189a950390a973fdfce94f56190de92db
2006-11-30Load the hypervisor symbols twice, once with an address mask so that we can ↵Ali Saidi
get symbols for where it's copied to in memory Add the ability to use an address mask for symbol loading Rather then silently failing on platform accesses panic Move BadAddr/IsaFake no Device from Tsunami Let the system kernel be none, but warn about it configs/common/FSConfig.py: We don't have a kernel for sparc yet src/arch/sparc/system.cc: Load the hypervisor symbols twice, once with an address mask so that we can get symbols for where it's copied to in memory src/base/loader/aout_object.cc: src/base/loader/aout_object.hh: src/base/loader/ecoff_object.cc: src/base/loader/ecoff_object.hh: src/base/loader/elf_object.cc: src/base/loader/elf_object.hh: src/base/loader/object_file.hh: src/base/loader/raw_object.cc: src/base/loader/raw_object.hh: Add the ability to use an address mask for symbol loading src/dev/sparc/t1000.cc: Rather then silently failing on platform accesses panic src/dev/sparc/t1000.hh: fix up a couple of platform comments src/python/m5/objects/Bus.py: src/python/m5/objects/Device.py: src/python/m5/objects/T1000.py: src/python/m5/objects/Tsunami.py: Move BadAddr/IsaFake no Device from Tsunami src/python/m5/objects/System.py: Let kernel be none src/sim/system.cc: Let the system kernel be none, but warn about it --HG-- extra : convert_revision : 92f6afef599a3d3c7c5026d03434102c41c7b5f4
2006-11-23Merge zizzer:/bk/sparcfsAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : f540987901994fe9dc023587fd555efb2dbf24bf
2006-11-23first cut at a sparc tlbAli Saidi
src/arch/sparc/SConscript: Add code to serialize/unserialze tlb entries src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: update asi names for how they're listed in the supplement add asis add more asi functions src/arch/sparc/isa_traits.hh: move the interrupt stuff and some basic address space stuff into isa traits src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: add mmu registers to tlb get rid of implicit asi stuff... the tlb will handle it src/arch/sparc/regfile.hh: make isnt/dataAsid return ints not asis src/arch/sparc/tlb.cc: src/arch/sparc/tlb.hh: first cut at sparc tlb src/arch/sparc/vtophys.hh: pagatable nedes to be included here src/mem/request.hh: add asi and if the request is a memory mapped register to the requset object src/sim/host.hh: fix incorrect definition of LL --HG-- extra : convert_revision : 6c85cd1681c62c8cd8eab04f70b1f15a034b0aa3
2006-11-16add warn_once which will print any given warning messageNathan Binkert
only once. --HG-- extra : convert_revision : b64bb495c1bd0c4beb3db6ca28fad5af4d05ef8e
2006-11-11set TRACING_ON one way or another explicitly in theNathan Binkert
SConscript file instead of basing it on DEBUG --HG-- extra : convert_revision : 6e6807cc4350ef92baeaaabfeb3dc0bb785128ba
2006-11-10fix endian issues with condition codesAli Saidi
use memcpy instead of bcopy s/u_int32_t/uint32_t/g fixup endian code to work with solaris hack to make sure htole() works... Nate, have a good idea to fix this? src/arch/sparc/faults.cc: set the reset address to be 40 bits. Makes PC printing easier at least for now. src/arch/sparc/isa/base.isa: fix endian issues with condition codes src/arch/sparc/tlb.hh: add implemented physical addres constants src/arch/sparc/utility.hh: add tlb.hh to utilities src/base/loader/raw_object.cc: add a symbol <filename>_start to the symbol table for binaries files src/base/remote_gdb.cc: use memcpy instead of bcopy src/cpu/exetrace.cc: clean up printing a bit more src/cpu/m5legion_interface.h: add tons to the shared interface src/dev/ethertap.cc: s/u_int32_t/uint32_t/g src/dev/ide_atareg.h: fixup endian code to work with solaris src/dev/pcidev.cc: src/sim/param.hh: hack to make sure htole() works... --HG-- extra : convert_revision : 4579392184b40bcc1062671a953c6595c685e9b2
2006-11-09Get SPARC to the point that it starts running. Add ability to load the ROM ↵Ali Saidi
bin files, cleanup lockstep printing a bit Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work. SConstruct: Add TARGET_ISA to the list of environment variables that end up in the build_env for python configs/common/FSConfig.py: add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now src/SConscript: add a raw file object, at least until we get more info about how to compile openboot properly src/arch/sparc/system.cc: src/arch/sparc/system.hh: add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM src/base/loader/object_file.cc: src/base/loader/object_file.hh: add option to try raw when nothing works src/cpu/exetrace.cc: cleanup lockstep printing a little bit src/cpu/m5legion_interface.h: change the instruction to be 32 bits because it is src/mem/physical.cc: fix assert that doesn't work if memory starts somewhere above 0 src/python/m5/objects/BaseCPU.py: Add if statement to choose between sparc tlbs and alpha tlbs src/python/m5/objects/System.py: Add a sparc system that sets the rom addresses correctly src/python/m5/params.py: add the ability to add Addr() together --HG-- extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af
2006-11-08Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops --HG-- extra : convert_revision : dc165840841bdd88e40111b98d1be493441703f0
2006-11-08Make a function to say how big gdbregs is in bytes vs. regs.Gabe Black
--HG-- extra : convert_revision : 10c50c2d45a8e510d71cccde520059363116da8a
2006-11-08DWARF2 symbol support seems to be broken on Solaris. Use stabs+Ali Saidi
align the character arrays that are used by placement-new for classes lest we have an unaligned fault on SPARC/Solaris src/SConscript: DWARF2 symbol support seems to be broken on Solaris. Use stabs+ src/base/statistics.hh: align the character arrays that are used by placement-new for classes lest we have an unaligned fault on SPARC/Solaris --HG-- extra : convert_revision : bc875a4fdfb4553062d3278537bc32a5ab9b6cca
2006-11-07Broke remote_gdb into a base class and architecture specific derived classes.Gabe Black
--HG-- extra : convert_revision : 8c528fab56a95b8245ad0f2572d62bb556ce0dde
2006-11-06Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops src/SConscript: SCCS merged --HG-- extra : convert_revision : f130c8a2d33f58d857e5d5a02bb9698c1bceb23b
2006-11-06Remote GDB support has been changed to use inheritance. Alpha should work, ↵Gabe Black
but isn't tested. Other architectures will not. --HG-- extra : convert_revision : fc7e1e73e2f3b1a4ab9905a1eb98c5f07c6c8707
2006-11-06Created seperate SConscript for the dev directory. Made subdirectories for ↵Gabe Black
Alpha and SPARC and put SConscripts in them. --HG-- rename : src/base/kgdb.h => src/arch/alpha/kgdb.h rename : src/dev/alpha_access.h => src/dev/alpha/access.h rename : src/dev/alpha_console.cc => src/dev/alpha/console.cc rename : src/dev/alpha_console.hh => src/dev/alpha/console.hh extra : convert_revision : a7dd466308cb83edc40528689aacb72413089cdf
2006-11-04fixes so that M5 will compile under solarisAli Saidi
SConstruct: Add check to see if we need to include libsocket src/arch/sparc/floatregfile.cc: src/arch/sparc/intregfile.cc: use memset rather than bzero and include the appropriate headerfile src/base/pollevent.cc: If we're compling under solaris we need sys/file.h src/base/random.cc: src/base/random.hh: solaris doesn't have random(), so use rint with the correct rounding mode if we're compiling on solaris src/base/stats/flags.hh: u_int32_t?? src/base/time.hh: grab the timersub() define from freebsd since it doesn't exist in solaris src/cpu/inst_seq.hh: we don't need to include stdint here src/sim/byteswap.hh: the method to detect endianness on Solaris is a little more complex... --HG-- extra : convert_revision : 6b7db0e900e7bccfc250d65c125065f27280dda1
2006-10-27Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : ec35a9276ae21e0b9fe820bd700c020e4440a350
2006-10-26Added a few functions to stuff values into bitfields in an instruction.Gabe Black
--HG-- extra : convert_revision : 507d7e13fd6276acf36b75eba31dff5e8080113f
2006-10-24Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem.head --HG-- extra : convert_revision : 4db140e6e8408b3ed39da327515b8e88a2701e6b
2006-10-24Add more traceflags for ethernetAli Saidi
--HG-- extra : convert_revision : a5025f501d72626d1bcb4dcc24ee353ceb160ce7
2006-10-23Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem --HG-- extra : convert_revision : cb15101d24ef2969e1819d6bdeeb2dd1f23f02d1
2006-10-23Files in base shouldn't depend on things in sim. Changed "sim/host.hh" to ↵Gabe Black
<inttypes.hh> --HG-- extra : convert_revision : c1e46c012a26cdb0603416f8e8a99e0ecb1c09bc
2006-10-21Add Quiesce trace flag to track CPU quiesce/wakeup events.Steve Reinhardt
--HG-- extra : convert_revision : 23be99d0fe6e2184523efe5d9e0a1ac7bf19d087
2006-10-19Add "All" compund flag to enable all defined trace flags.Steve Reinhardt
--HG-- extra : convert_revision : dcc699d8341f762dee659290cd35206e326e1179
2006-10-12Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem.head src/mem/packet.hh: hand merge --HG-- extra : convert_revision : 3f77707360235dc98c6b12a0367ca64a401313df
2006-10-12add a traceflag for functional accessesAli Saidi
implement fix packet and add the ability to print a packet to a ostream remove tabs in packet.hh (Could people stop inserting them??!?!?!) mark const functions in packet.hh as such src/base/traceflags.py: add a traceflag for functional accesses src/mem/packet.cc: implement fix packet and add the ability to print a packet to a ostream src/mem/packet.hh: add the ability to print a packet to an ostream remove tabs in file mark const functions as such --HG-- extra : convert_revision : 4297bce5e1d3abbab48be5bd9eb9e982b751fc7c
2006-10-12Fix problems with unCacheable addresses in timing-coherenceRon Dreslinski
src/base/traceflags.py: src/mem/physical.cc: Add debug falgs fro physical memory accesses src/mem/cache/cache_impl.hh: Snoops to uncacheable blocks should not happen src/mem/cache/miss/miss_queue.cc: Set the size properly on unCacheable accesses --HG-- extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
2006-10-10Debugging infoRon Dreslinski
src/base/traceflags.py: Add new flags for cacheport src/mem/bus.cc: Add debugging info src/mem/cache/base_cache.cc: Add debuggin info --HG-- extra : convert_revision : a6c4b452466a8e0b50a86e886833cb6e29edc748
2006-10-08Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)Steve Reinhardt
and PhysicalMemory. *No* support for caches or O3CPU. Note that properly setting cpu_id on all CPUs is now required for correct operation. src/arch/SConscript: src/base/traceflags.py: src/cpu/base.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: src/python/m5/objects/BaseCPU.py: tests/configs/simple-atomic.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. --HG-- extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
2006-09-11add annotation code to m5Ali Saidi
configs/common/Benchmarks.py: add annotate test app src/SConscript: add annotate.cc to lis src/arch/alpha/isa/decoder.isa: add annotate instructions src/base/traceflags.py: Add annotate trace flag src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: add annotate pseudo ops util/m5/m5op.S: util/m5/m5op.h: add anotate ops --HG-- extra : convert_revision : 7f965c0d84e41ce34f2ec8ec27a009276d67d8d6
2006-08-28Fix remote gdb buffer overflow.Steve Reinhardt
--HG-- extra : convert_revision : e5e5206bdd48120cebcb1e339b1dab2e10f4b6cf
2006-08-15fixes for gcc 4.1Ali Saidi
Nate needs to fix sinic builder stuff Gabe needs to verify my fixes to decoder.isa OPT/DEBUG compiles for ALPHA_FS, ALPHA_SE, MIPS_SE, SPARC_SE with this changeset README: Fix the swig version in the readme src/SConscript: remove sinic until nate fixes the builder crap for it src/arch/alpha/system.hh: src/arch/mips/isa/includes.isa: src/arch/sparc/isa/decoder.isa: src/base/stats/visit.cc: src/base/timebuf.hh: src/dev/ide_disk.cc: src/dev/sinic.cc: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr_queue.cc: src/mem/packet.hh: src/mem/request.hh: src/sim/builder.hh: src/sim/system.hh: fixes for gcc 4.1 --HG-- extra : convert_revision : 3775427c0047b282574d4831dd602c96cac3ba17
2006-08-15Some touchup to the reorganized includes and "using" directives.Gabe Black
--HG-- extra : convert_revision : 956c80d6d826b08e52c0892a480a0a9b74b96b9d
2006-08-14Fix up doxygen.Steve Reinhardt
--HG-- rename : docs/footer.html => src/doxygen/footer.html rename : docs/stl.hh => src/doxygen/stl.hh extra : convert_revision : 2b2e5637930843c1be07deaa708fd4126213cda2
2006-08-11Added code to support setting up all of the auxillieary vectors configured ↵Gabe Black
by the sparc linux elf loader. src/arch/sparc/process.cc: All of the auxilliary vectors are now set like they are in the linux elf loader. This code should probably be moved to arch/sparc/linux/process.cc somehow. --HG-- extra : convert_revision : 4a90cacf70b1032cad3f18b0f833a6df8237e0de
2006-07-10Add parameters for backwards and forwards sizes for time buffers.Kevin Lim
src/base/timebuf.hh: Add a function to return the size of the time buffer. --HG-- extra : convert_revision : 8ffacd8b9013eb76264df065244e00dc1460efd4
2006-07-05Fix up some merge problems.Kevin Lim
src/base/traceflags.py: Remove BaseCPU traceflag. src/cpu/o3/alpha/params.hh: Move non-Alpha specific parameters out of this params class. src/cpu/o3/params.hh: Move non-Alpha specific params into this params class. --HG-- extra : convert_revision : e5b652adb47a240376733400e6054c66c50bd514
2006-07-05Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge src/base/traceflags.py: src/cpu/SConscript: Hand merge. src/cpu/o3/alpha/params.hh: Hand merge. This needs to get changed. --HG-- rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py extra : convert_revision : 581f338f5bce35288f7d15d95cbd0ac3a9135e6a
2006-07-05Alphabetize traceflags, rename FullCPUAll flag to O3CPUAll.Kevin Lim
--HG-- extra : convert_revision : f558966154376223674c82d513afc2dad6591426
2006-07-02Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)Korey Sewell
Edit Test3 for newmem src/base/traceflags.py: Add O3CPU flag src/cpu/base.cc: for some reason adding a BaseCPU flag doesnt work so just go back to old way... src/cpu/o3/alpha/cpu_builder.cc: Determine number threads by workload size instead of solely by parameter. Default SMT fetch policy to RoundRobin if it's not specified in Config file src/cpu/o3/commit.hh: only use nextNPC for !ALPHA src/cpu/o3/commit_impl.hh: add FetchTrapPending as condition for commit src/cpu/o3/cpu.cc: panic if active threads is more than Impl::MaxThreads src/cpu/o3/fetch.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: name stuff src/cpu/o3/fetch_impl.hh: fatal if try to use SMT branch count, that's unimplemented right now src/python/m5/config.py: make it clearer that a parameter is not valid within a configuration class --HG-- extra : convert_revision : 55069847304e40e257f9225f0dc3894ce6491b34
2006-07-01traceflag stuffKorey Sewell
src/base/traceflags.py: add BaseCPU flag, O3CPUAll flag grouping src/cpu/base.cc: Use BaseCPU flag instead of FullCPU flag --HG-- extra : convert_revision : 32f737a2f58eb936634799f1f809e07cbba90179
2006-06-26remove extern "C" from the functions we all from gdb. This isn't requried ↵Ali Saidi
and trips up GDB sometimes when i thinks the extern name should be mangled, but it isn't --HG-- extra : convert_revision : 62e2a1989e8fd3d73958d3a3e2d00e378488e642
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 20:43:34 +0000