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Also some bug fixes in MIPS ISA uncovered by g++ warnings
(Python string compares don't work in C++!).
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file with them all.
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Signed Off: Ali Saidi <saidi@eecs.umich.edu>
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LoadAddrMask correctly for x86.
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This works in SE mode because the virtual and physical addresses specified for
segments are the same. In Alpha, the LoadAddrMask is still necessary because
the virtual and physical addresses are the same and apparently rely on the
super page mechanism. All of the regressions pass.
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way so a cache can handle partial block requests for i/o devices.
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These haven't been very thuroughly tested, so use at your own risk.
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Previously, the bitunion would need to be declared and then assigned to separately.
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into vm1.(none):/home/stever/bk/newmem-cache2
src/base/traceflags.py:
Hand merge.
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src/arch/mips/SConscript:
"mips import pt.1".
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configs/example/memtest.py:
Add progress interval option.
src/base/traceflags.py:
Add MemTest flag.
src/cpu/memtest/memtest.cc:
Clean up tracing.
src/cpu/memtest/memtest.hh:
Get rid of unused code.
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it with FreeBSD's implementation
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not sum the operands and then apply the operation.
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fewer bits than last, bit_val << last would get the wrong answer.
src/base/bitfield.hh:
bit_val was being used directly in the statement in
return. If type B had fewer bits than last, bit_val << last would get
the wrong answer.
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not a cpp file because c99
(which defines fenv) doesn't necessarily extend to c++ and it is a problem with solaris. If really
desired this could wrap the ieeefp interface found in bsd* as well, but I see no need at the moment.
src/arch/alpha/isa/fp.isa:
src/arch/sparc/isa/formats/basic.isa:
use m5_fesetround()/m5_fegetround() istead of fenv interface directly
src/arch/sparc/isa/includes.isa:
use base/fenv instead of fenv directly
src/base/SConscript:
add fenv to sconscript
src/base/fenv.hh:
src/base/random.cc:
m5 implementation to standerdize fenv across platforms.
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and python code into m5 to allow swig an python code to
easily added by any SConscript instead of just the one in
src/python. This provides SwigSource and PySource for
adding new files to m5 (similar to Source for C++). Also
provides SimObject for including files that contain SimObject
information and build the m5.objects __init__.py file.
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just directly exec the file and generate the flags
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rename : src/arch/x86/isa/decoder.isa => src/arch/x86/isa/decoder/decoder.isa
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sign extend themselves.
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