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2007-08-03merge from headSteve Reinhardt
--HG-- extra : convert_revision : 21f7afe2719c00744c0981212c1ee6e442238e01
2007-08-02Output: Make OutputDirectory::create() be able to create binary files.Ali Saidi
--HG-- extra : convert_revision : eae114ee5f27bb8b319df705d9b39bded185b8e8
2007-07-22Merge more changes in from head.Steve Reinhardt
--HG-- extra : convert_revision : 8f170f2754eccdb424a35b5b077225abcf6eee72
2007-07-22Merge Gabe's changes with mine.Steve Reinhardt
--HG-- extra : convert_revision : f50ed42e7acb3f11e610fd6976eaa8df0c6ba2ab
2007-07-20Fix function which calculates the carry flag.Gabe Black
--HG-- extra : convert_revision : aeb4f2d4c3936089421dbe80647f28ae36178283
2007-07-18Fix a compilation error for SubBitUnions,Gabe Black
--HG-- extra : convert_revision : aad9388afe81ba6541d0b18fa9777e6ffcfd871c
2007-07-17Create a file of functions for computing condition codes.Gabe Black
These haven't been very thuroughly tested, so use at your own risk. --HG-- extra : convert_revision : 938885d36fea4a99f8228cdf195a0e0a38dd9031
2007-07-17Add a conversion constructor so a bitunion can be initialized to a value.Gabe Black
Previously, the bitunion would need to be declared and then assigned to separately. --HG-- extra : convert_revision : d229bd83bc7baeca2259d4e7b080f359915015f3
2007-07-14Move bitunion code into it's own file.Gabe Black
--HG-- extra : convert_revision : 8d55ca9645ee4e357b7f4595435542eb72490331
2007-07-14Add CacheRepl trace flag and move a couple DPRINTFs to it.Steve Reinhardt
--HG-- extra : convert_revision : 31724d19ebdf2cdc2a2bafff83d17845b3a0b183
2007-07-14Merge from head.Steve Reinhardt
--HG-- extra : convert_revision : f7b3700762b796d44f99aef05783db1ee9c7412e
2007-07-14Make NO_FAST_ALLOC compile.Steve Reinhardt
--HG-- extra : convert_revision : 80579a61eb8d220e75cdee11bc09ca985c8fd85c
2007-06-23Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 src/base/traceflags.py: Hand merge. --HG-- extra : convert_revision : 9e7539eeab4220ed7a7237457a8f336f79216924
2007-06-22mips import pt. 1Korey Sewell
src/arch/mips/SConscript: "mips import pt.1". --HG-- extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
2007-06-21Getting closer...Steve Reinhardt
configs/example/memtest.py: Add progress interval option. src/base/traceflags.py: Add MemTest flag. src/cpu/memtest/memtest.cc: Clean up tracing. src/cpu/memtest/memtest.hh: Get rid of unused code. --HG-- extra : convert_revision : 92bd8241a6c90bfb6d908e5a5132cbdb500cbb87
2007-06-14Fix an assert to allow rounding mode 0.Gabe Black
--HG-- extra : convert_revision : 119cc87ccf939d3a0048d87d18e125deca378bb7
2007-06-09only compile fenv.c if we're using fenvNathan Binkert
--HG-- extra : convert_revision : 990726f724f99505fc999af82bfb1bbcd6c7f1a2
2007-05-26Get rid of GNU libelf and its autoconf nastiness and replaceNathan Binkert
it with FreeBSD's implementation --HG-- extra : convert_revision : ef9c4551b9a6b54b76a89f286ff9804c55790621
2007-05-11total should be the sum of the vector result of an operation,Nathan Binkert
not sum the operands and then apply the operation. --HG-- extra : convert_revision : 06486e59b3dd9588b458ef45c341cc4f2554dc09
2007-05-09bit_val was being used directly in the statement in return. If type B had ↵Ali Saidi
fewer bits than last, bit_val << last would get the wrong answer. src/base/bitfield.hh: bit_val was being used directly in the statement in return. If type B had fewer bits than last, bit_val << last would get the wrong answer. --HG-- extra : convert_revision : cbc43ccd139f82ebbd65f30af5d05b87c4edac64
2007-04-21fixes for solaris compileAli Saidi
--HG-- extra : convert_revision : c82a62a61650e3700d237da917c453e5a9676320
2007-04-21create base/fenv.c to standerdize fenv across platforms. It's a c file and ↵Ali Saidi
not a cpp file because c99 (which defines fenv) doesn't necessarily extend to c++ and it is a problem with solaris. If really desired this could wrap the ieeefp interface found in bsd* as well, but I see no need at the moment. src/arch/alpha/isa/fp.isa: src/arch/sparc/isa/formats/basic.isa: use m5_fesetround()/m5_fegetround() istead of fenv interface directly src/arch/sparc/isa/includes.isa: use base/fenv instead of fenv directly src/base/SConscript: add fenv to sconscript src/base/fenv.hh: src/base/random.cc: m5 implementation to standerdize fenv across platforms. --HG-- extra : convert_revision : 38d2629affd964dcd1a5ab0db4ac3cb21438e72c
2007-04-12Completely re-work how the scons framework incorporates swigNathan Binkert
and python code into m5 to allow swig an python code to easily added by any SConscript instead of just the one in src/python. This provides SwigSource and PySource for adding new files to m5 (similar to Source for C++). Also provides SimObject for including files that contain SimObject information and build the m5.objects __init__.py file. --HG-- extra : convert_revision : 38b50a0629846ef451ed02f96fe3633947df23eb
2007-03-26Instead of creating a new python process to run traceflags.py,Nathan Binkert
just directly exec the file and generate the flags --HG-- extra : convert_revision : d648ca7348404ded5337db327adafccbd2ae40c8
2007-03-21Missed a constGabe Black
--HG-- rename : src/arch/x86/isa/decoder.isa => src/arch/x86/isa/decoder/decoder.isa extra : convert_revision : a60e7495da6fe99fa2375a3f801f2962c3e41adb
2007-03-20Fixed up some types and const placement, and added signed bitfields that ↵Gabe Black
sign extend themselves. --HG-- extra : convert_revision : 84bda8fc14f9a6f7dc7982c9aeb15bf688457706
2007-03-19Ditched read or write only subbitfields for now since they were proving ↵Gabe Black
difficult to implement. Allow component Bitfields to be instantiated without templates, clean up the implementation a little, and adjust the comments to match. --HG-- extra : convert_revision : b9b8aea285a95eeabbb4c0233c1bce49b8c773b8
2007-03-19For the _BitfieldRO and _BitfieldWO classes, make sure the undesired ↵Gabe Black
operator is redefined as private. --HG-- extra : convert_revision : b18d8e49547c2712ab255d048850c5231313b80a
2007-03-19Formatting fixes.Gabe Black
--HG-- extra : convert_revision : 276d0667daa4626288b56af3b4b17a3f9052e81a
2007-03-19Lots and lots of comments.Gabe Black
--HG-- extra : convert_revision : 0de510464e2e002775ccd79e2922ccb0055845e5
2007-03-19Reworked the BitUnion stuff a bit. There is moderately better isolation of ↵Gabe Black
the backend parts, although there are still macros. --HG-- extra : convert_revision : e9692c5e697c96061ef70cf78ef532c99dbbd672
2007-03-17Created BitUnion type which lets you define nested bitfields for an integer ↵Gabe Black
in a portable way. --HG-- extra : convert_revision : 56a9d06b6b7274a493dae4b290c5f9b42e59f20d
2007-03-15Merge zizzer:/bk/newmemAli Saidi
into pb15.local:/Users/ali/work/m5.newmem --HG-- extra : convert_revision : 0aa2fadf8978ae30ebe4fde03c525e6b9115117a
2007-03-15fix a bug gabe foundAli Saidi
--HG-- extra : convert_revision : 12e8f09f6c59a16b2d2eb78bdd1345fc38c4de40
2007-03-15Changed warns to DPRINTFs and multiply by 8 where needed.Gabe Black
--HG-- extra : convert_revision : 9db0bc2420ceb5828a79881fa0b420a2d5e5f358
2007-03-13Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace --HG-- extra : convert_revision : 61eca737296a5ce839d3b97f047b4fda062cb899
2007-03-13fix interrupting during a quisce on sparcAli Saidi
src/arch/sparc/ua2005.cc: fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to check if were suspended and interrupt at the guess time src/base/traceflags.py: add trace flag for Iob src/cpu/simple/base.cc: Use Quisce instead of IPI trace flag src/dev/sparc/iob.cc: add some Dprintfs --HG-- extra : convert_revision : 72e18fcc750ad1e4b2bb67b19b354eaffc6af6d5
2007-03-12call ccprintf() with the appropriate argument types so we don't recuse foreverAli Saidi
--HG-- extra : convert_revision : 5366be897d1193cf9e93b1fcd0689d19783f73a8
2007-03-12remove the extern C around gdb helper functions. It's need needed for any ↵Ali Saidi
new version of gdb to work and it causes at least mine to segfault --HG-- extra : convert_revision : 5e4c2ec753372fd0569734d3ddb0c8690409ca16
2007-03-12Get rid of those pesky valgrind warnings, Conditional jump or move depends ↵Ali Saidi
on uninitialised value(s), in the stats package --HG-- extra : convert_revision : d3a508fc98df4eb8160a211a306be6ab241a4ce8
2007-03-11Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace --HG-- extra : convert_revision : 725999a0a5bde6e065bad87b42e973c5c627c69f
2007-03-11Make sttw and sttwa use the twin memory operations.Gabe Black
--HG-- extra : convert_revision : 368d1c57a46fd5ca15461cb5ee8e05fd1e080daa
2007-03-10Rework the way SCons recurses into subdirectories, making itNathan Binkert
automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. --HG-- extra : convert_revision : 103f6b490d2eb224436688c89cdc015211c4fd30
2007-03-07Add some constructors and an output operator to the Twin??_t types so that ↵Gabe Black
o3 SPARC will compile again. --HG-- extra : convert_revision : af987aaeac87ee92a3b55cf0839d994cf7dea1af
2007-03-06Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 0822fbcc377781b53d2de9ba40ab9d985ccbc039
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. --HG-- extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
2007-03-06Get X86 to load an elf and start a process for it.Gabe Black
src/arch/x86/SConscript: Add in process source files. src/arch/x86/isa_traits.hh: Replace magic constant numbers with the x86 register names. src/arch/x86/miscregfile.cc: Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy. src/arch/x86/process.hh: An X86 process class. src/base/loader/elf_object.cc: Add in code to recognize x86 as an architecture. src/base/traceflags.py: Add an x86 traceflag src/sim/process.cc: Add in code to create an x86 process. src/arch/x86/intregs.hh: A file which declares names for the integer register indices. src/arch/x86/linux/linux.cc: src/arch/x86/linux/linux.hh: A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either. src/arch/x86/linux/process.cc: src/arch/x86/linux/process.hh: An x86 linux process. The syscall table is split out into it's own file. src/arch/x86/linux/syscalls.cc: The x86 Linux syscall table and the uname function. src/arch/x86/process.cc: The x86 process base class. tests/test-progs/hello/bin/x86/linux/hello: An x86 hello world test binary. --HG-- extra : convert_revision : f22919e010c07aeaf5757dca054d9877a537fd08
2007-03-05Add x86 to the Arch enum in the object file class.Gabe Black
--HG-- extra : convert_revision : bc8c5e78aac0e9033d6cbc756d8092369ac29072
2007-03-03Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : fd6464c9883783c7c2cbefba317f4a0f20dd24cb
2007-03-03Implement Niagara I/O interface and rework interruptsAli Saidi
configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore --HG-- extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 20:54:22 +0000