Age | Commit message (Collapse) | Author |
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Its only purpose was to print the cycle number but that already
happens in the SIGABRT handler. No one used it anyway.
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each time.
This appears to work, but I don't want to commit it until it gets tested a lot more.
I haven't deleted the functionality in this patch that will come later, but one question
is how to enforce encourage objects that call getVirtPort() to not cache the virtual port
since if the CPU changes out from under them it will be worse than useless. Perhaps a null
function like delVirtPort() is still useful in that case.
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Make sure variables are properly initialized and also make sure that
truth testing works properly.
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classes.
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Make OutputDirectory::resolve() private and change the functions using
resolve() to instead use create().
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Also some bug fixes in MIPS ISA uncovered by g++ warnings
(Python string compares don't work in C++!).
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file with them all.
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Signed Off: Ali Saidi <saidi@eecs.umich.edu>
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LoadAddrMask correctly for x86.
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This works in SE mode because the virtual and physical addresses specified for
segments are the same. In Alpha, the LoadAddrMask is still necessary because
the virtual and physical addresses are the same and apparently rely on the
super page mechanism. All of the regressions pass.
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way so a cache can handle partial block requests for i/o devices.
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These haven't been very thuroughly tested, so use at your own risk.
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Previously, the bitunion would need to be declared and then assigned to separately.
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into vm1.(none):/home/stever/bk/newmem-cache2
src/base/traceflags.py:
Hand merge.
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src/arch/mips/SConscript:
"mips import pt.1".
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configs/example/memtest.py:
Add progress interval option.
src/base/traceflags.py:
Add MemTest flag.
src/cpu/memtest/memtest.cc:
Clean up tracing.
src/cpu/memtest/memtest.hh:
Get rid of unused code.
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