gem5 - gem5

Age	Commit message (Expand)	Author
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-10-15	Regression: Use CPU clock and 32-byte width for L1-L2 bus	Andreas Hansson
2012-09-25	sim: Move CPU-specific methods from SimObject to the BaseCPU class	Andreas Sandberg
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-21	CPU: Remove overloaded function_trace_start parameter	Andreas Hansson
2012-08-21	Clock: Move the clock and related functions to ClockedObject	Andreas Hansson
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-03-01	x86: Fix switching of CPUs	Nilay Vaish
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-17	CPU: Moving towards a more general port across CPU models	Andreas Hansson
2012-01-07	Merge with the main repository again.	Gabe Black
2011-12-01	ARM: Add support for having a TLB cache.	Ali Saidi
2011-11-18	SE/FS: Get rid of FULL_SYSTEM in the CPU directory.	Gabe Black
2011-11-02	SE/FS: Get rid of FULL_SYSTEM in sim.	Gabe Black
2011-10-16	ARM: Turn on the page table walker on ARM in SE mode.	Gabe Black
2011-10-13	X86: Turn on the page table walker in SE mode.	Gabe Black
2011-10-09	SE/FS: Build the Interrupt objects in SE mode.	Gabe Black
2011-03-26	mips: cleanup ISA-specific code	Korey Sewell
2011-02-06	mcpat: Adds McPAT performance counters	Joel Hestness
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
2011-02-01	X86: Add L1 caches for the TLB walkers.	Gabe Black
2010-11-23	X86: Loosen an assert for x86 and connect the APIC ports when caches are used.	Gabe Black
2010-06-02	ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.	Ali Saidi
2009-10-27	POWER: Add support for the Power ISA	Timothy M. Jones
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
2009-04-21	arm: Unify the ARM tlb. We forgot about this when we did the rest.	Nathan Binkert
2009-04-08	tlb: More fixing of unified TLB	Nathan Binkert
2009-04-08	tlb: Don't separate the TLB classes into an instruction TLB and a data TLB	Gabe Black
2009-01-30	Config: Cause a fatal() when a parameter without a default value isn't set(FS...	Ali Saidi
2008-12-17	Make Alpha pseudo-insts available from SE mode.	Steve Reinhardt
2008-11-02	make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered	Lisa Hsu
2008-10-12	X86: Fix the ordering of special physical address ranges.	Gabe Black
2008-10-12	X86: Make APICs communicate through the memory system.	Gabe Black
2008-10-12	X86: Make the local APIC accessible through the memory system directly, and m...	Gabe Black
2008-10-12	Turn Interrupts objects into SimObjects. Also, move local APIC state into x86...	Gabe Black
2008-08-11	params: Convert the CPU objects to use the auto generated param structs.	Nathan Binkert
2008-02-05	Add base ARM code to M5	Stephen Hines
2007-11-21	imported patch pagewalker.patch	Gabe Black
2007-11-13	Add in files from merge-bare-iron, get them compiling in FS and SE mode	Korey Sewell
2007-08-26	Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.	Gabe Black
2007-08-08	Added fastmem option.	Vincentius Robby
2007-07-28	Turn the instruction tracing code into pluggable sim objects.	Gabe Black
2007-05-27	Move SimObject python files alongside the C++ and fix	Nathan Binkert