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path: root/src/cpu/BaseCPU.py
AgeCommit message (Expand)Author
2017-05-02python: Use PyBind11 instead of SWIG for Python wrappersAndreas Sandberg
2015-07-20syscall_emul: [patch 13/22] add system call retry capabilityBrandon Potter
2016-11-30arch: [Patch 1/5] Added RISC-V base instruction set RV64IAlec Roelke
2016-04-05cpu: Query CPU for inst executed from PythonGeoffrey Blake
2015-09-30isa,cpu: Add support for FS SMT InterruptsMitch Hayenga
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
2015-03-02arm: Share a port for the two table walker objectsAndreas Hansson
2015-01-25cpu: Put all CPU instruction tracers in a single fileAli Saidi
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-05-09cpu, arm: Allow the specification of a socket fieldAkash Bagdia
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2013-09-04cpu: Move the branch predictor out of the BaseCPUAndreas Hansson
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-27config: Remove redundant explicit setting of default clocksAkash Bagdia
2013-06-11cpu: Add support for scheduling multiple inst/load stop eventsAndreas Sandberg
2013-04-22cpu: Let python scripts obtain the number of instructions executedTimothy M. Jones
2013-04-22cpu: generate SimPoint basic block vector profilesDam Sunwoo
2013-02-19x86: Move APIC clock divider to PythonAndreas Hansson
2013-02-15cpu: Add CPU metadata om the Python classesAndreas Sandberg
2013-01-24branch predictor: move out of o3 and inorder cpusNilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-07cpu: Flush TLBs on switchOut()Andreas Sandberg
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07cpu: Introduce sanity checks when switching between CPUsAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-10-15Regression: Use CPU clock and 32-byte width for L1-L2 busAndreas Hansson
2012-09-25sim: Move CPU-specific methods from SimObject to the BaseCPU classAndreas Sandberg
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-21CPU: Remove overloaded function_trace_start parameterAndreas Hansson
2012-08-21Clock: Move the clock and related functions to ClockedObjectAndreas Hansson
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-03-01x86: Fix switching of CPUsNilay Vaish
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-28Merge with the main repo.Gabe Black
2012-01-17CPU: Moving towards a more general port across CPU modelsAndreas Hansson
2012-01-07Merge with the main repository again.Gabe Black
2011-12-01ARM: Add support for having a TLB cache.Ali Saidi
2011-11-18SE/FS: Get rid of FULL_SYSTEM in the CPU directory.Gabe Black
2011-11-02SE/FS: Get rid of FULL_SYSTEM in sim.Gabe Black
2011-10-16ARM: Turn on the page table walker on ARM in SE mode.Gabe Black
2011-10-13X86: Turn on the page table walker in SE mode.Gabe Black
2011-10-09SE/FS: Build the Interrupt objects in SE mode.Gabe Black
2011-03-26mips: cleanup ISA-specific codeKorey Sewell
2011-02-06mcpat: Adds McPAT performance countersJoel Hestness
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2011-02-01X86: Add L1 caches for the TLB walkers.Gabe Black
2010-11-23X86: Loosen an assert for x86 and connect the APIC ports when caches are used.Gabe Black