gem5 - gem5

Age	Commit message (Expand)	Author
2017-05-02	python: Use PyBind11 instead of SWIG for Python wrappers	Andreas Sandberg
2015-07-20	syscall_emul: [patch 13/22] add system call retry capability	Brandon Potter
2016-11-30	arch: [Patch 1/5] Added RISC-V base instruction set RV64I	Alec Roelke
2016-04-05	cpu: Query CPU for inst executed from Python	Geoffrey Blake
2015-09-30	isa,cpu: Add support for FS SMT Interrupts	Mitch Hayenga
2015-03-02	mem: Move crossbar default latencies to subclasses	Andreas Hansson
2015-03-02	arm: Share a port for the two table walker objects	Andreas Hansson
2015-01-25	cpu: Put all CPU instruction tracers in a single file	Ali Saidi
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
2014-05-09	cpu, arm: Allow the specification of a socket field	Akash Bagdia
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2013-09-04	cpu: Move the branch predictor out of the BaseCPU	Andreas Hansson
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-06-27	config: Remove redundant explicit setting of default clocks	Akash Bagdia
2013-06-11	cpu: Add support for scheduling multiple inst/load stop events	Andreas Sandberg
2013-04-22	cpu: Let python scripts obtain the number of instructions executed	Timothy M. Jones
2013-04-22	cpu: generate SimPoint basic block vector profiles	Dam Sunwoo
2013-02-19	x86: Move APIC clock divider to Python	Andreas Hansson
2013-02-15	cpu: Add CPU metadata om the Python classes	Andreas Sandberg
2013-01-24	branch predictor: move out of o3 and inorder cpus	Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-07	cpu: Flush TLBs on switchOut()	Andreas Sandberg
2013-01-07	cpu: Rename defer_registration->switched_out	Andreas Sandberg
2013-01-07	cpu: Introduce sanity checks when switching between CPUs	Andreas Sandberg
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-10-15	Regression: Use CPU clock and 32-byte width for L1-L2 bus	Andreas Hansson
2012-09-25	sim: Move CPU-specific methods from SimObject to the BaseCPU class	Andreas Sandberg
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-21	CPU: Remove overloaded function_trace_start parameter	Andreas Hansson
2012-08-21	Clock: Move the clock and related functions to ClockedObject	Andreas Hansson
2012-05-31	Bus: Split the bus into a non-coherent and coherent bus	Andreas Hansson
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-03-01	x86: Fix switching of CPUs	Nilay Vaish
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-17	CPU: Moving towards a more general port across CPU models	Andreas Hansson
2012-01-07	Merge with the main repository again.	Gabe Black
2011-12-01	ARM: Add support for having a TLB cache.	Ali Saidi
2011-11-18	SE/FS: Get rid of FULL_SYSTEM in the CPU directory.	Gabe Black
2011-11-02	SE/FS: Get rid of FULL_SYSTEM in sim.	Gabe Black
2011-10-16	ARM: Turn on the page table walker on ARM in SE mode.	Gabe Black
2011-10-13	X86: Turn on the page table walker in SE mode.	Gabe Black
2011-10-09	SE/FS: Build the Interrupt objects in SE mode.	Gabe Black
2011-03-26	mips: cleanup ISA-specific code	Korey Sewell
2011-02-06	mcpat: Adds McPAT performance counters	Joel Hestness
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
2011-02-01	X86: Add L1 caches for the TLB walkers.	Gabe Black
2010-11-23	X86: Loosen an assert for x86 and connect the APIC ports when caches are used.	Gabe Black