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path: root/src/cpu/BaseCPU.py
AgeCommit message (Expand)Author
2019-10-19cpu,arm: Push the stage 2 MMUs out of the CPU into the TLBs.Gabe Black
2019-10-19arch: Make a base class for Interrupts.Gabe Black
2019-10-18cpu: Turn the stage 2 ARM MMUs from params to children.Gabe Black
2019-10-17cpu: Get rid of load count based events.Gabe Black
2019-08-10cpu: Pull more arch specialization to the top of BaseCPU.py.Gabe Black
2019-08-10x86: Move some fixed or dummy config information into X86LocalApic.py.Gabe Black
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-02-22python: Fix param -> int conversion issuesAndreas Sandberg
2019-02-22python: Make iterator handling Python 3 compatibleAndreas Sandberg
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
2018-03-06scons: Switch from the print statement to the print function.Gabe Black
2018-01-29arm: DT autogeneration - Generate cpus nodeGlenn Bergmans
2018-01-12sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().Xiaoyu Ma
2018-01-11cpu: Make the CPU's TLB parameter a BaseTLB.Gabe Black
2017-11-29cpu: Don't override ISA if provided by userAndreas Sandberg
2017-11-20cpu: Make automatic transition to OFF optionalJose Marinho
2017-11-20pwr: Adds logic to enter power gating for the cpu modelAnouk Van Laer
2017-07-12cpu, sim: Add param to force CPUs to wait for GDBJose Marinho
2017-05-02python: Use PyBind11 instead of SWIG for Python wrappersAndreas Sandberg
2015-07-20syscall_emul: [patch 13/22] add system call retry capabilityBrandon Potter
2016-11-30arch: [Patch 1/5] Added RISC-V base instruction set RV64IAlec Roelke
2016-04-05cpu: Query CPU for inst executed from PythonGeoffrey Blake
2015-09-30isa,cpu: Add support for FS SMT InterruptsMitch Hayenga
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
2015-03-02arm: Share a port for the two table walker objectsAndreas Hansson
2015-01-25cpu: Put all CPU instruction tracers in a single fileAli Saidi
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-05-09cpu, arm: Allow the specification of a socket fieldAkash Bagdia
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2013-09-04cpu: Move the branch predictor out of the BaseCPUAndreas Hansson
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-27config: Remove redundant explicit setting of default clocksAkash Bagdia
2013-06-11cpu: Add support for scheduling multiple inst/load stop eventsAndreas Sandberg
2013-04-22cpu: Let python scripts obtain the number of instructions executedTimothy M. Jones
2013-04-22cpu: generate SimPoint basic block vector profilesDam Sunwoo
2013-02-19x86: Move APIC clock divider to PythonAndreas Hansson
2013-02-15cpu: Add CPU metadata om the Python classesAndreas Sandberg
2013-01-24branch predictor: move out of o3 and inorder cpusNilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-07cpu: Flush TLBs on switchOut()Andreas Sandberg
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07cpu: Introduce sanity checks when switching between CPUsAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-10-15Regression: Use CPU clock and 32-byte width for L1-L2 busAndreas Hansson
2012-09-25sim: Move CPU-specific methods from SimObject to the BaseCPU classAndreas Sandberg
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-21CPU: Remove overloaded function_trace_start parameterAndreas Hansson
2012-08-21Clock: Move the clock and related functions to ClockedObjectAndreas Hansson
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
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