| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-03-14 | arch-arm,cpu: Add initial support for Arm SVE | Giacomo Gabrielli |
| 2018-10-09 | arch-arm: AArch32 Crypto AES | Matt Horsnell |
| 2018-10-09 | arch-arm: AArch32 Crypto SHA | Matt Horsnell |
| 2016-10-15 | cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass | Fernando Endo |
| 2015-04-29 | cpu: o3: replace issueLatency with bool pipelined | Nilay Vaish |
| 2012-11-02 | sim: Include object header files in SWIG interfaces | Andreas Sandberg |
| 2012-09-07 | Param: Transition to Cycles for relevant parameters | Andreas Hansson |
| 2010-11-15 | CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. | Giacomo Gabrielli |
| 2007-06-11 | Rename enum from OpType to OpClass so it's consistent with the | Nathan Binkert |
| 2007-05-27 | Move SimObject python files alongside the C++ and fix | Nathan Binkert |
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