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path: root/src/cpu/SConscript
AgeCommit message (Expand)Author
2014-07-23cpu: `Minor' in-order CPU modelAndrew Bardsley
2014-05-09cpu: Add flag name printing to StaticInstAndrew Bardsley
2013-10-15cpu: clean up architectural register classificationSteve Reinhardt
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-02-15cpu: Document exec trace flagsAndreas Sandberg
2012-11-02cpu: Add header files for checker CPUsAndreas Sandberg
2012-05-26ISA,CPU: Generalize and split out the components of the decode cache.Gabe Black
2012-05-25ISA: Make the decode function part of the ISA's decoder.Gabe Black
2012-05-25Decode: Make the Decoder class defined per ISA.Gabe Black
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2011-11-18SE/FS: Get rid of FULL_SYSTEM in the CPU directory.Gabe Black
2011-10-31SE/FS: Make the functions available from the TC consistent between SE and FS.Gabe Black
2011-09-30SE/FS: Build the devices in SE mode.Gabe Black
2011-09-09Decode: Pull instruction decoding out of the StaticInst class into its own.Gabe Black
2011-07-15O3: Create a pipeline activity viewer for the O3 CPU model.Giacomo Gabrielli
2011-06-02scons: rename TraceFlags to DebugFlagsNathan Binkert
2011-05-13Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.Chander Sudanthi
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2010-11-19SCons: Support building without an ISAAli Saidi
2010-11-15SCons: Cleanup SCons output during compileAli Saidi
2010-02-26cpu_models: get rid of cpu_models.py and move the stuff into SConsNathan Binkert
2009-09-26O3: Add flag to control whether faulting instructions are traced.Steve Reinhardt
2009-07-19CPU: Separate out native trace into ISA (in)dependent code and SimObjects.Gabe Black
2009-06-04move: put predictor includes and cc files into the same placeNathan Binkert
2009-05-12inorder-tlb-cunit: merge the TLB as implicit to any memory accessKorey Sewell
2009-05-12inorder-o3: allow both to compile togetherKorey Sewell
2009-05-12inorder/alpha-isa: create eaComp object visible to StaticInst through ISAKorey Sewell
2009-04-18o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ...Korey Sewell
2009-02-10CPU: Prepare CPU models for the new in-order CPU model.Korey Sewell
2009-01-13SCons: centralize the Dir() workaround for newer versions of scons.Nathan Binkert
2009-01-06Tracing: Make tracing aware of macro and micro ops.Gabe Black
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
2008-04-10SCons: add comments to SConscript documenting bug workaroundAli Saidi
2008-04-08SCons: Manually specifying header only directories with Dir() works around th...Ali Saidi
2007-11-08CPU: Add function to explictly compare thread contexts after copying.Ali Saidi
2007-10-31Traceflags: Add SCons function to created a traceflag instead of having one f...Ali Saidi
2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
2007-03-10Rework the way SCons recurses into subdirectories, making itNathan Binkert
2007-01-26make our code a little more standards compliantAli Saidi
2006-10-09Update the Memtester, commit a config file/test for it.Ron Dreslinski
2006-07-21Minor functionality updates.Kevin Lim
2006-07-19Put regression tests back into m5. They are located in the "tests" directory...Kevin Lim
2006-07-14Fix the CheckerCPU being included via python.Kevin Lim
2006-07-10Some minor cleanups.Kevin Lim
2006-07-05Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-05Split off files that are shared across the O3 and Ozone models.Kevin Lim