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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
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path:
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src
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cpu
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SConscript
Age
Commit message (
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Author
2013-02-15
cpu: Document exec trace flags
Andreas Sandberg
2012-11-02
cpu: Add header files for checker CPUs
Andreas Sandberg
2012-05-26
ISA,CPU: Generalize and split out the components of the decode cache.
Gabe Black
2012-05-25
ISA: Make the decode function part of the ISA's decoder.
Gabe Black
2012-05-25
Decode: Make the Decoder class defined per ISA.
Gabe Black
2012-03-09
CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Geoffrey Blake
2012-01-31
Merge with head, hopefully the last time for this batch.
Gabe Black
2012-01-31
CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
Geoffrey Blake
2011-11-18
SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
Gabe Black
2011-10-31
SE/FS: Make the functions available from the TC consistent between SE and FS.
Gabe Black
2011-09-30
SE/FS: Build the devices in SE mode.
Gabe Black
2011-09-09
Decode: Pull instruction decoding out of the StaticInst class into its own.
Gabe Black
2011-07-15
O3: Create a pipeline activity viewer for the O3 CPU model.
Giacomo Gabrielli
2011-06-02
scons: rename TraceFlags to DebugFlags
Nathan Binkert
2011-05-13
Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.
Chander Sudanthi
2011-04-15
trace: reimplement the DTRACE function so it doesn't use a vector
Nathan Binkert
2010-11-19
SCons: Support building without an ISA
Ali Saidi
2010-11-15
SCons: Cleanup SCons output during compile
Ali Saidi
2010-02-26
cpu_models: get rid of cpu_models.py and move the stuff into SCons
Nathan Binkert
2009-09-26
O3: Add flag to control whether faulting instructions are traced.
Steve Reinhardt
2009-07-19
CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
Gabe Black
2009-06-04
move: put predictor includes and cc files into the same place
Nathan Binkert
2009-05-12
inorder-tlb-cunit: merge the TLB as implicit to any memory access
Korey Sewell
2009-05-12
inorder-o3: allow both to compile together
Korey Sewell
2009-05-12
inorder/alpha-isa: create eaComp object visible to StaticInst through ISA
Korey Sewell
2009-04-18
o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ...
Korey Sewell
2009-02-10
CPU: Prepare CPU models for the new in-order CPU model.
Korey Sewell
2009-01-13
SCons: centralize the Dir() workaround for newer versions of scons.
Nathan Binkert
2009-01-06
Tracing: Make tracing aware of macro and micro ops.
Gabe Black
2008-08-11
params: Convert the CPU objects to use the auto generated param structs.
Nathan Binkert
2008-04-10
SCons: add comments to SConscript documenting bug workaround
Ali Saidi
2008-04-08
SCons: Manually specifying header only directories with Dir() works around th...
Ali Saidi
2007-11-08
CPU: Add function to explictly compare thread contexts after copying.
Ali Saidi
2007-10-31
Traceflags: Add SCons function to created a traceflag instead of having one f...
Ali Saidi
2007-07-28
Turn the instruction tracing code into pluggable sim objects.
Gabe Black
2007-07-23
Major changes to how SimObjects are created and initialized. Almost all
Nathan Binkert
2007-05-27
Move SimObject python files alongside the C++ and fix
Nathan Binkert
2007-03-10
Rework the way SCons recurses into subdirectories, making it
Nathan Binkert
2007-01-26
make our code a little more standards compliant
Ali Saidi
2006-10-09
Update the Memtester, commit a config file/test for it.
Ron Dreslinski
2006-07-21
Minor functionality updates.
Kevin Lim
2006-07-19
Put regression tests back into m5. They are located in the "tests" directory...
Kevin Lim
2006-07-14
Fix the CheckerCPU being included via python.
Kevin Lim
2006-07-10
Some minor cleanups.
Kevin Lim
2006-07-05
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-07-05
Split off files that are shared across the O3 and Ozone models.
Kevin Lim
2006-06-30
Make O3CPU model independent of the ISA
Korey Sewell
2006-06-22
Changes to get OzoneCPU to compile once more.
Kevin Lim
2006-06-22
Split Checker up properly into templated and non-templated definitions.
Kevin Lim
2006-06-22
Fix to have the static inst exec sigs also dependent on the CPU models used.
Kevin Lim
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