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path: root/src/cpu/base.cc
AgeCommit message (Expand)Author
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-06-06pwr: Low-power idle power state for idle CPUsDavid Guillen Fandos
2016-06-06sim: Call regStats of base-class as wellStephan Diestelhorst
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2014-12-09power: Low-power idle power state for idle CPUsAkash Bagdia
2016-04-05cpu: Query CPU for inst executed from PythonGeoffrey Blake
2015-11-27base: Add support for changing output directoriesAndreas Sandberg
2016-02-06style: eliminate explicit boolean comparisonsSteve Reinhardt
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2015-11-20cpu: Enforce 1 interrupt controller per threadAndreas Sandberg
2015-09-30isa,cpu: Add support for FS SMT InterruptsMitch Hayenga
2015-09-30cpu: Add per-thread monitorsMitch Hayenga
2015-09-30cpu: Change thread assignments for heterogenous SMTMitch Hayenga
2015-08-21cpu: Move invldPid constant from Request to BaseCPUAndreas Hansson
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-04-14config, cpu: fix progress interval for switched CPUsMalek Musleh
2015-01-10cpu: fix RetiredStores probe pointNikos Nikoleris
2014-11-14arm: Fixes based on UBSan and static analysisAndreas Hansson
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-10-16cpu: Probe points for basic PMU statsAndreas Sandberg
2014-05-09arch, arm: Preserve TLB bootUncacheability when switching CPUsGeoffrey Blake
2014-05-09cpu, arm: Allow the specification of a socket fieldAkash Bagdia
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-06-11cpu: Add support for scheduling multiple inst/load stop eventsAndreas Sandberg
2013-04-22cpu: generate SimPoint basic block vector profilesDam Sunwoo
2013-03-26cpu: Remove CpuPort and use MasterPort in the CPU classesAndreas Hansson
2013-02-15cpu: Refactor memory system checksAndreas Sandberg
2013-01-07cpu: Unify the serialization code for all of the CPU modelsAndreas Sandberg
2013-01-07cpu: Flush TLBs on switchOut()Andreas Sandberg
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07cpu: Introduce sanity checks when switching between CPUsAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2012-11-02ARM: dump stats and process info on context switchesDam Sunwoo
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-09-12Base CPU: Initialize profileEvent to NULLJoel Hestness
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-08-28Port: Stricter port bind/unbind semanticsAndreas Hansson
2012-08-21Clock: Move the clock and related functions to ClockedObjectAndreas Hansson
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-07-09Fix: Address a few benign memory leaksAndreas Hansson
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
2012-02-12cpu: add separate stats for insts/ops both globally and per cpu modelAnthony Gutierrez
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
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