| Age | Commit message (Expand) | Author |
|---|
| 2018-06-21 | cpu: Fix bug introduced by RequestPtr type change | Giacomo Travaglini |
| 2018-06-11 | misc: Using smart pointers for memory Requests | Giacomo Travaglini |
| 2018-04-27 | sim,cpu,mem,arch: Introduced MasterInfo data structure | Giacomo Travaglini |
| 2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
| 2017-11-21 | cpu, cpu, sim: move Cycle probe update | Jose Marinho |
| 2017-11-20 | cpu: Make automatic transition to OFF optional | Jose Marinho |
| 2017-11-20 | pwr: Adds logic to enter power gating for the cpu model | Anouk Van Laer |
| 2017-07-12 | cpu: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | cpu, sim: Add param to force CPUs to wait for GDB | Jose Marinho |
| 2017-06-20 | cpu, gpu-compute: Replace EventWrapper use with EventFunctionWrapper | Sean Wilson |
| 2015-07-20 | syscall_emul: [patch 13/22] add system call retry capability | Brandon Potter |
| 2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter |
| 2016-06-06 | pwr: Low-power idle power state for idle CPUs | David Guillen Fandos |
| 2016-06-06 | sim: Call regStats of base-class as well | Stephan Diestelhorst |
| 2016-04-06 | Revert power patch sets with unexpected interactions | Andreas Sandberg |
| 2014-12-09 | power: Low-power idle power state for idle CPUs | Akash Bagdia |
| 2016-04-05 | cpu: Query CPU for inst executed from Python | Geoffrey Blake |
| 2015-11-27 | base: Add support for changing output directories | Andreas Sandberg |
| 2016-02-06 | style: eliminate explicit boolean comparisons | Steve Reinhardt |
| 2016-02-06 | style: fix missing spaces in control statements | Steve Reinhardt |
| 2015-11-20 | cpu: Enforce 1 interrupt controller per thread | Andreas Sandberg |
| 2015-09-30 | isa,cpu: Add support for FS SMT Interrupts | Mitch Hayenga |
| 2015-09-30 | cpu: Add per-thread monitors | Mitch Hayenga |
| 2015-09-30 | cpu: Change thread assignments for heterogenous SMT | Mitch Hayenga |
| 2015-08-21 | cpu: Move invldPid constant from Request to BaseCPU | Andreas Hansson |
| 2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
| 2015-04-14 | config, cpu: fix progress interval for switched CPUs | Malek Musleh |
| 2015-01-10 | cpu: fix RetiredStores probe point | Nikos Nikoleris |
| 2014-11-14 | arm: Fixes based on UBSan and static analysis | Andreas Hansson |
| 2014-11-06 | x86 isa: This patch attempts an implementation at mwait. | Marc Orr |
| 2014-10-16 | cpu: Probe points for basic PMU stats | Andreas Sandberg |
| 2014-05-09 | arch, arm: Preserve TLB bootUncacheability when switching CPUs | Geoffrey Blake |
| 2014-05-09 | cpu, arm: Allow the specification of a socket field | Akash Bagdia |
| 2013-11-25 | sim: simulate with multiple threads and event queues | Steve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E) |
| 2013-07-18 | mem: Set the cache line size on a system level | Andreas Hansson |
| 2013-06-11 | cpu: Add support for scheduling multiple inst/load stop events | Andreas Sandberg |
| 2013-04-22 | cpu: generate SimPoint basic block vector profiles | Dam Sunwoo |
| 2013-03-26 | cpu: Remove CpuPort and use MasterPort in the CPU classes | Andreas Hansson |
| 2013-02-15 | cpu: Refactor memory system checks | Andreas Sandberg |
| 2013-01-07 | cpu: Unify the serialization code for all of the CPU models | Andreas Sandberg |
| 2013-01-07 | cpu: Flush TLBs on switchOut() | Andreas Sandberg |
| 2013-01-07 | cpu: Rename defer_registration->switched_out | Andreas Sandberg |
| 2013-01-07 | cpu: Introduce sanity checks when switching between CPUs | Andreas Sandberg |
| 2013-01-07 | arch: Make the ISA class inherit from SimObject | Andreas Sandberg |
| 2012-11-02 | ARM: dump stats and process info on context switches | Dam Sunwoo |
| 2012-10-15 | Port: Add protocol-agnostic ports in the port hierarchy | Andreas Hansson |
| 2012-09-12 | Base CPU: Initialize profileEvent to NULL | Joel Hestness |
| 2012-08-28 | Clock: Rework clocks to avoid tick-to-cycle transformations | Andreas Hansson |
| 2012-08-28 | Port: Stricter port bind/unbind semantics | Andreas Hansson |
