gem5 - gem5

Age	Commit message (Expand)	Author
2009-02-16	Fixes to get prefetching working again.	Steve Reinhardt
2009-01-25	CPU: Add a setCPU function to the interrupt objects.	Gabe Black
2009-01-24	cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep.	Nathan Binkert
2008-11-05	Right now a single thread cpu 1 could get assigned context Id != 1, depending	Lisa Hsu
2008-11-04	get rid of all instances of readTid() and getThreadNum(). Unify and eliminate	Lisa Hsu
2008-11-02	Add in Context IDs to the simulator. From now on, cpuId is almost never used,	Lisa Hsu
2008-11-02	Make it so that all thread contexts are registered with the System, even in	Lisa Hsu
2008-11-02	make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered	Lisa Hsu
2008-10-21	style: Use the correct m5 style for things relating to interrupts.	Nathan Binkert
2008-10-12	Turn Interrupts objects into SimObjects. Also, move local APIC state into x86...	Gabe Black
2008-10-12	CPU: Eliminate the get_vec function.	Gabe Black
2008-10-09	eventq: convert all usage of events to use the new API.	Nathan Binkert
2008-08-18	Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was ...	Richard Strong
2008-08-11	params: Convert the CPU objects to use the auto generated param structs.	Nathan Binkert
2008-06-15	port: Clean up default port setup and port switchover code.	Nathan Binkert
2008-02-06	Make the Event::description() a const function	Stephen Hines
2007-12-18	Checkpointing: Fix a bug in the simulation script when restoring without stan...	Ali Saidi
2007-11-08	CPU: Add function to explictly compare thread contexts after copying.	Ali Saidi
2007-09-28	Rename cycles() function to ticks()	Ali Saidi
2007-08-30	params: Deprecate old-style constructors; update most SimObject constructors.	Miles Kaufmann
2007-08-04	switching: turn on profiling after a switch if there's an event	Nathan Binkert
2007-07-29	Merge Gabe's changes from head.	Steve Reinhardt
2007-07-29	BsaeCPU: Get rid of some bad DPRINTFs.	Steve Reinhardt
2007-07-28	Turn the instruction tracing code into pluggable sim objects.	Gabe Black
2007-07-26	Merge python and x86 changes with cache branch	Nathan Binkert
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-06-30	Event descriptions should not end in "event"	Steve Reinhardt
2007-06-20	Removed "adding instead of dividing" trick.	Vincentius Robby
2007-05-20	Add new EventWrapper constructor that takes a Tick value	Steve Reinhardt
2007-03-23	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2007-03-23	Set progress_interval in terms of CPU cycles.	Kevin Lim
2007-03-09	Two fixes:	Kevin Lim
2007-03-03	Implement Niagara I/O interface and rework interrupts	Ali Saidi
2007-02-17	Give the progress event its own priority	Nathan Binkert
2007-01-30	Make SPARC checkpointing work	Ali Saidi
2007-01-26	eliminate cpu checkInterrupts bool, it is redundant and unnecessary.	Lisa Hsu
2007-01-08	the way i understand it, interrupts in m5 is a little bloated. the usage of ...	Lisa Hsu
2006-12-04	More changes to get SPARC fs closer. Now at 1.2M cycles before difference	Ali Saidi
2006-11-14	Make cpu's capable of having a phase shift	Ron Dreslinski
2006-11-06	Merge zizzer.eecs.umich.edu:/bk/newmem/	Gabe Black
2006-11-06	Clean up clock phase drift code a bit.	Kevin Lim
2006-11-03	Add a new file which describes an ISA's interrupt handling mechanism. It reco...	Gabe Black
2006-10-06	there are two main thrusts of this changeset.	Lisa Hsu
2006-10-02	Updates to fix merge issues and bring almost everything up to working speed. ...	Kevin Lim
2006-09-30	Merge ktlim@zamp:./local/clean/o3-merge/m5	Kevin Lim
2006-07-10	Fix cpu in full system to match SE.	Ron Dreslinski
2006-07-07	Update cpus to use the getPort function to use a connector object to connect ...	Ron Dreslinski
2006-07-05	Remove sampler and serializer. Now they are handled through C++ interacting ...	Kevin Lim
2006-07-02	Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)	Korey Sewell
2006-07-01	traceflag stuff	Korey Sewell