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path: root/src/cpu/base.cc
AgeCommit message (Expand)Author
2009-01-24cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep.Nathan Binkert
2008-11-05Right now a single thread cpu 1 could get assigned context Id != 1, dependingLisa Hsu
2008-11-04get rid of all instances of readTid() and getThreadNum(). Unify and eliminateLisa Hsu
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-11-02Make it so that all thread contexts are registered with the System, even inLisa Hsu
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
2008-10-21style: Use the correct m5 style for things relating to interrupts.Nathan Binkert
2008-10-12Turn Interrupts objects into SimObjects. Also, move local APIC state into x86...Gabe Black
2008-10-12CPU: Eliminate the get_vec function.Gabe Black
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-08-18Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was ...Richard Strong
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
2008-06-15port: Clean up default port setup and port switchover code.Nathan Binkert
2008-02-06Make the Event::description() a const functionStephen Hines
2007-12-18Checkpointing: Fix a bug in the simulation script when restoring without stan...Ali Saidi
2007-11-08CPU: Add function to explictly compare thread contexts after copying.Ali Saidi
2007-09-28Rename cycles() function to ticks()Ali Saidi
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
2007-08-04switching: turn on profiling after a switch if there's an eventNathan Binkert
2007-07-29Merge Gabe's changes from head.Steve Reinhardt
2007-07-29BsaeCPU: Get rid of some bad DPRINTFs.Steve Reinhardt
2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-06-30Event descriptions should not end in "event"Steve Reinhardt
2007-06-20Removed "adding instead of dividing" trick.Vincentius Robby
2007-05-20Add new EventWrapper constructor that takes a Tick valueSteve Reinhardt
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
2007-03-23Set progress_interval in terms of CPU cycles.Kevin Lim
2007-03-09Two fixes:Kevin Lim
2007-03-03Implement Niagara I/O interface and rework interruptsAli Saidi
2007-02-17Give the progress event its own priorityNathan Binkert
2007-01-30Make SPARC checkpointing workAli Saidi
2007-01-26eliminate cpu checkInterrupts bool, it is redundant and unnecessary.Lisa Hsu
2007-01-08the way i understand it, interrupts in m5 is a little bloated. the usage of ...Lisa Hsu
2006-12-04More changes to get SPARC fs closer. Now at 1.2M cycles before differenceAli Saidi
2006-11-14Make cpu's capable of having a phase shiftRon Dreslinski
2006-11-06Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
2006-11-06Clean up clock phase drift code a bit.Kevin Lim
2006-11-03Add a new file which describes an ISA's interrupt handling mechanism. It reco...Gabe Black
2006-10-06there are two main thrusts of this changeset.Lisa Hsu
2006-10-02Updates to fix merge issues and bring almost everything up to working speed. ...Kevin Lim
2006-09-30Merge ktlim@zamp:./local/clean/o3-merge/m5Kevin Lim
2006-07-10Fix cpu in full system to match SE.Ron Dreslinski
2006-07-07Update cpus to use the getPort function to use a connector object to connect ...Ron Dreslinski
2006-07-05Remove sampler and serializer. Now they are handled through C++ interacting ...Kevin Lim
2006-07-02Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)Korey Sewell
2006-07-01traceflag stuffKorey Sewell
2006-06-29Various fixes for the CPU models to support the features that have been moved...Kevin Lim
2006-06-09Merge vm1.(none):/home/stever/bk/newmemSteve Reinhardt
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