| Age | Commit message (Expand) | Author |
|---|
| 2017-11-20 | cpu: Make automatic transition to OFF optional | Jose Marinho |
| 2017-11-20 | pwr: Adds logic to enter power gating for the cpu model | Anouk Van Laer |
| 2017-07-12 | cpu: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | cpu, sim: Add param to force CPUs to wait for GDB | Jose Marinho |
| 2015-07-20 | syscall_emul: [patch 13/22] add system call retry capability | Brandon Potter |
| 2016-06-06 | pwr: Low-power idle power state for idle CPUs | David Guillen Fandos |
| 2016-04-07 | mem: Remove threadId from memory request class | Mitch Hayenga |
| 2016-04-06 | Revert power patch sets with unexpected interactions | Andreas Sandberg |
| 2016-04-05 | mem: Remove threadId from memory request class | Mitch Hayenga |
| 2014-12-09 | power: Low-power idle power state for idle CPUs | Akash Bagdia |
| 2016-04-05 | cpu: Query CPU for inst executed from Python | Geoffrey Blake |
| 2015-10-12 | misc: Add explicit overrides and fix other clang >= 3.5 issues | Andreas Hansson |
| 2015-10-12 | misc: Remove redundant compiler-specific defines | Andreas Hansson |
| 2015-09-30 | cpu,isa,mem: Add per-thread wakeup logic | Mitch Hayenga |
| 2015-09-30 | isa,cpu: Add support for FS SMT Interrupts | Mitch Hayenga |
| 2015-09-30 | cpu: Add per-thread monitors | Mitch Hayenga |
| 2015-08-21 | cpu: Move invldPid constant from Request to BaseCPU | Andreas Hansson |
| 2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
| 2015-01-25 | cpu: remove legion tracer | Ali Saidi |
| 2014-11-06 | x86 isa: This patch attempts an implementation at mwait. | Marc Orr |
| 2014-10-16 | cpu: Probe points for basic PMU stats | Andreas Sandberg |
| 2014-09-20 | cpu: Remove unused deallocateContext calls | Mitch Hayenga |
| 2014-09-20 | alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate | Mitch Hayenga |
| 2014-05-09 | cpu, arm: Allow the specification of a socket field | Akash Bagdia |
| 2014-03-07 | cpu: Make CPU and ThreadContext getters const | Andreas Hansson |
| 2014-01-24 | cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo... | Ali Saidi |
| 2013-09-04 | arch: Resurrect the NOISA build target and rename it NULL | Andreas Hansson |
| 2013-07-19 | cpu: Remove unused getBranchPred() method from BaseCPU | Andreas Sandberg |
| 2013-07-18 | mem: Set the cache line size on a system level | Andreas Hansson |
| 2013-06-11 | cpu: Add support for scheduling multiple inst/load stop events | Andreas Sandberg |
| 2013-04-22 | kvm: Avoid synchronizing the TC on every KVM exit | Andreas Sandberg |
| 2013-03-26 | cpu: Remove CpuPort and use MasterPort in the CPU classes | Andreas Hansson |
| 2013-02-15 | cpu: Refactor memory system checks | Andreas Sandberg |
| 2013-01-07 | cpu: Unify the serialization code for all of the CPU models | Andreas Sandberg |
| 2013-01-07 | cpu: Flush TLBs on switchOut() | Andreas Sandberg |
| 2013-01-07 | cpu: Introduce sanity checks when switching between CPUs | Andreas Sandberg |
| 2012-11-02 | ARM: dump stats and process info on context switches | Dam Sunwoo |
| 2012-10-15 | Port: Add protocol-agnostic ports in the port hierarchy | Andreas Hansson |
| 2012-09-25 | sim: Move CPU-specific methods from SimObject to the BaseCPU class | Andreas Sandberg |
| 2012-08-28 | Clock: Add a Cycles wrapper class and use where applicable | Andreas Hansson |
| 2012-08-21 | Clock: Move the clock and related functions to ClockedObject | Andreas Hansson |
| 2012-05-26 | CPU: Merge the predecoder and decoder. | Gabe Black |
| 2012-05-01 | MEM: Separate requests and responses for timing accesses | Andreas Hansson |
| 2012-04-14 | MEM: Separate snoops and normal memory requests/responses | Andreas Hansson |
| 2012-04-03 | Atomic: Remove the physmem_port and access memory directly | Andreas Hansson |
| 2012-03-30 | MEM: Introduce the master/slave port sub-classes in C++ | William Wang |
| 2012-03-19 | clang: Fix recently introduced clang compilation errors | Andreas Hansson |
| 2012-03-02 | CPU: Check that the interrupt controller is created when needed | Andreas Hansson |
| 2012-02-24 | CPU: Round-two unifying instr/data CPU ports across models | Andreas Hansson |
| 2012-02-12 | cpu: add separate stats for insts/ops both globally and per cpu model | Anthony Gutierrez |
