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gem5
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invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
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path:
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src
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cpu
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base.hh
Age
Commit message (
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)
Author
2012-02-12
cpu: add separate stats for insts/ops both globally and per cpu model
Anthony Gutierrez
2012-02-12
mem: Add a master ID to each request object.
Ali Saidi
2012-01-31
Merge with head, hopefully the last time for this batch.
Gabe Black
2012-01-31
clang: Enable compiling gem5 using clang 2.9 and 3.0
Koan-Sin Tan
2012-01-28
Merge with the main repo.
Gabe Black
2012-01-16
Merge yet again with the main repository.
Gabe Black
2012-01-17
MEM: Separate queries for snooping and address ranges
Andreas Hansson
2012-01-17
CPU: Moving towards a more general port across CPU models
Andreas Hansson
2012-01-09
O3: Add support of function tracing with O3 CPU.
Ali Saidi
2011-11-18
SE/FS: Get rid of includes of config/full_system.hh.
Gabe Black
2011-11-18
SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
Gabe Black
2011-11-01
SE/FS: Expose the same methods on the CPUs in SE and FS modes.
Gabe Black
2011-10-09
SE/FS: Build the Interrupt objects in SE mode.
Gabe Black
2011-04-15
includes: sort all includes
Nathan Binkert
2011-03-26
mips: cleanup ISA-specific code
Korey Sewell
2011-02-06
m5: added work completed monitoring support
Brad Beckmann
2011-02-06
mcpat: Adds McPAT performance counters
Joel Hestness
2011-01-07
Replace curTick global variable with accessor functions.
Steve Reinhardt
2010-11-15
O3: Make O3 support variably lengthed instructions.
Gabe Black
2010-04-15
tick: rename Clock namespace to SimClock
Nathan Binkert
2010-01-12
since totalInstructions() is impl'ed by all the cpus, make it an abstract bas...
Lisa Hsu
2009-09-23
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
Nathan Binkert
2009-05-26
types: add a type for thread IDs and try to use it everywhere
Nathan Binkert
2009-05-05
cpus: fix cpu progress event
Korey Sewell
2009-03-05
stats: Fix all stats usages to deal with template fixes
Nathan Binkert
2009-01-24
cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep.
Nathan Binkert
2008-11-04
get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
Lisa Hsu
2008-11-02
make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
Lisa Hsu
2008-10-21
style: Use the correct m5 style for things relating to interrupts.
Nathan Binkert
2008-10-12
CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
Gabe Black
2008-10-12
Turn Interrupts objects into SimObjects. Also, move local APIC state into x86...
Gabe Black
2008-10-12
CPU: Eliminate the get_vec function.
Gabe Black
2008-10-11
CPU: Add a getInterruptController function
Gabe Black
2008-10-09
eventq: convert all usage of events to use the new API.
Nathan Binkert
2008-08-18
Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was ...
Richard Strong
2008-08-11
params: Convert the CPU objects to use the auto generated param structs.
Nathan Binkert
2008-02-06
Make the Event::description() a const function
Stephen Hines
2007-11-15
add core specific parameter to BaseCPU params
Korey Sewell
2007-11-13
Add in files from merge-bare-iron, get them compiling in FS and SE mode
Korey Sewell
2007-09-28
Rename cycles() function to ticks()
Ali Saidi
2007-09-28
Update statistics to use cycles properly instead of ticks
Ali Saidi
2007-07-28
Turn the instruction tracing code into pluggable sim objects.
Gabe Black
2007-03-15
Merge zizzer.eecs.umich.edu:/bk/newmem
Gabe Black
2007-03-15
Make the predecoder an object with it's own switched header file. Start addin...
Gabe Black
2007-03-09
Two fixes:
Kevin Lim
2007-03-03
Implement Niagara I/O interface and rework interrupts
Ali Saidi
2007-01-30
Make SPARC checkpointing work
Ali Saidi
2007-01-26
eliminate cpu checkInterrupts bool, it is redundant and unnecessary.
Lisa Hsu
2007-01-08
the way i understand it, interrupts in m5 is a little bloated. the usage of ...
Lisa Hsu
2006-12-04
More changes to get SPARC fs closer. Now at 1.2M cycles before difference
Ali Saidi
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