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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
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path:
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src
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cpu
/
base.hh
Age
Commit message (
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)
Author
2007-01-26
eliminate cpu checkInterrupts bool, it is redundant and unnecessary.
Lisa Hsu
2007-01-08
the way i understand it, interrupts in m5 is a little bloated. the usage of ...
Lisa Hsu
2006-12-04
More changes to get SPARC fs closer. Now at 1.2M cycles before difference
Ali Saidi
2006-11-14
Make cpu's capable of having a phase shift
Ron Dreslinski
2006-11-11
Get rid of the ParamContext for pseudo instructions and move
Nathan Binkert
2006-11-06
Merge zizzer.eecs.umich.edu:/bk/newmem/
Gabe Black
2006-11-06
Clean up clock phase drift code a bit.
Kevin Lim
2006-11-03
Got rid of "inPalMode". Some places are still effectively checking if they ar...
Gabe Black
2006-11-03
Add a new file which describes an ISA's interrupt handling mechanism. It reco...
Gabe Black
2006-10-08
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
Steve Reinhardt
2006-10-02
Updates to fix merge issues and bring almost everything up to working speed. ...
Kevin Lim
2006-09-30
Merge ktlim@zamp:./local/clean/o3-merge/m5
Kevin Lim
2006-07-07
Update cpus to use the getPort function to use a connector object to connect ...
Ron Dreslinski
2006-07-05
Remove sampler and serializer. Now they are handled through C++ interacting ...
Kevin Lim
2006-06-29
Various fixes for the CPU models to support the features that have been moved...
Kevin Lim
2006-06-06
Change ExecContext to ThreadContext. This is being renamed to differentiate ...
Kevin Lim
2006-06-02
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-05-31
Updated Authors from bk prs info
Ali Saidi
2006-05-30
Merge ktlim@zizzer:/bk/m5
Kevin Lim
2006-05-22
New directory structure:
Steve Reinhardt