gem5 - gem5

Age	Commit message (Expand)	Author
2014-01-24	cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...	Ali Saidi
2014-01-24	mem: per-thread cache occupancy and per-block ages	Dam Sunwoo
2013-10-17	cpu: Fix O3 uncacheable load that is replayed but misses the TLB	Ali Saidi
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-03-19	gcc: Clean-up of non-C++0x compliant code, first steps	Andreas Hansson
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-02-24	CPU: Round-two unifying instr/data CPU ports across models	Andreas Hansson
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-02-07	Faults: Turn off arch/faults.hh	Gabe Black
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2011-11-18	SE/FS: Get rid of includes of config/full_system.hh.	Gabe Black
2011-09-13	LSQ: Only trigger a memory violation with a load/load if the value changes.	Ali Saidi
2011-09-09	StaticInst: Merge StaticInst and StaticInstBase.	Gabe Black
2011-08-14	O3: Add a pointer to the macroop for a microop in the dyninst.	Gabe Black
2011-08-07	Translation: Use a pointer type as the template argument.	Gabe Black
2011-08-02	O3: Get rid of the raw ExtMachInst constructor on DynInsts.	Gabe Black
2011-07-02	ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.	Gabe Black
2011-07-02	ExecContext: Get rid of the now unused read/write templated functions.	Gabe Black
2011-04-04	CPU: Remove references to memory copy operations	Ali Saidi
2011-04-04	O3: Tighten memory order violation checking to 16 bytes.	Ali Saidi
2011-02-11	O3: Enhance data address translation by supporting hardware page table walkers.	Giacomo Gabrielli
2010-12-07	O3: Support squashing all state after special instruction	Ali Saidi
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-11-08	ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.	Ali Saidi
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-09-13	Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.	Gabe Black
2010-08-23	CPU: Make Exec trace to print predication result (if false) for memory instru...	Min Kyu Jeong
2010-08-23	ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.	Min Kyu Jeong
2010-08-23	CPU: Set a default value when readBytes faults.	Ali Saidi
2010-08-13	CPU: Add readBytes and writeBytes functions to the exec contexts.	Gabe Black
2010-02-20	BaseDynInst: Preserve the faults returned from read and write.	Timothy M. Jones
2010-02-12	O3PCU: Split loads and stores that cross cache line boundaries.	Timothy M. Jones
2010-02-12	BaseDynInst: Make the TLB translation timing instead of atomic.	Timothy M. Jones
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-08-01	Fix setting of INST_FETCH flag for O3 CPU.	Steve Reinhardt
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert
2009-04-08	tlb: More fixing of unified TLB	Nathan Binkert
2009-02-25	ISA: Replace the translate functions in the TLBs with translateAtomic.	Gabe Black
2009-02-25	CPU: Get rid of translate... functions from various interface classes.	Gabe Black
2008-11-10	O3CPU: Make the instcount debugging stuff per-cpu.	Clint Smullen
2008-11-02	Add in Context IDs to the simulator. From now on, cpuId is almost never used,	Lisa Hsu
2008-11-02	make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered	Lisa Hsu
2008-09-10	style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul...	Ali Saidi
2008-02-26	TLB: Make a TLB base class and put a virtual demapPage function in it.	Gabe Black
2007-10-22	CPU: Add functions to the "ExecContext"s that translate a given address.	Gabe Black
2007-08-26	O3 CPU: Remove alignment check from dynamic instruction read/write functions.	Gabe Black