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path: root/src/cpu/base_dyn_inst.hh
AgeCommit message (Expand)Author
2011-07-02ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.Gabe Black
2011-07-02ExecContext: Get rid of the now unused read/write templated functions.Gabe Black
2011-04-04CPU: Remove references to memory copy operationsAli Saidi
2011-04-04O3: Tighten memory order violation checking to 16 bytes.Ali Saidi
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
2010-12-07O3: Support squashing all state after special instructionAli Saidi
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-11-08ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
2010-08-23CPU: Make Exec trace to print predication result (if false) for memory instru...Min Kyu Jeong
2010-08-23ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.Min Kyu Jeong
2010-08-23CPU: Set a default value when readBytes faults.Ali Saidi
2010-08-13CPU: Add readBytes and writeBytes functions to the exec contexts.Gabe Black
2010-02-20BaseDynInst: Preserve the faults returned from read and write.Timothy M. Jones
2010-02-12O3PCU: Split loads and stores that cross cache line boundaries.Timothy M. Jones
2010-02-12BaseDynInst: Make the TLB translation timing instead of atomic.Timothy M. Jones
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-08-01Fix setting of INST_FETCH flag for O3 CPU.Steve Reinhardt
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-04-08tlb: More fixing of unified TLBNathan Binkert
2009-02-25ISA: Replace the translate functions in the TLBs with translateAtomic.Gabe Black
2009-02-25CPU: Get rid of translate... functions from various interface classes.Gabe Black
2008-11-10O3CPU: Make the instcount debugging stuff per-cpu.Clint Smullen
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
2008-09-10style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul...Ali Saidi
2008-02-26TLB: Make a TLB base class and put a virtual demapPage function in it.Gabe Black
2007-10-22CPU: Add functions to the "ExecContext"s that translate a given address.Gabe Black
2007-08-26O3 CPU: Remove alignment check from dynamic instruction read/write functions.Gabe Black
2007-07-31Add a flag to indicate an instruction triggers a syscall in SE mode.Gabe Black
2007-06-20Fix compiler errors.Gabe Black
2007-04-14Add support for microcode and pull out the special branch delay slot handling...Gabe Black
2007-04-13Remove most of the special handling for delay slots since they have to be squ...Gabe Black
2007-04-08Get the "hard" SPARC instructions working in o3. I don't like that the IsStor...Gabe Black
2007-03-23Two fixes:Kevin Lim
2006-12-28Implement a stub nnpc for alpha that is read only as npc+4.Gabe Black
2006-12-16Accidently "cleaned" away the NPC parameter to the constructor.Gabe Black
2006-12-16Added a predicted NPC field, explicitly stored whether the instruction was pr...Gabe Black
2006-12-12Merge zizzer:/bk/newmem/Gabe Black
2006-12-12Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(In...Steve Reinhardt
2006-12-06Get rid of some typedefs which were hardly used, and move some stuff back her...Gabe Black
2006-10-23Add in support for LL/SC in the O3 CPU. Needs to be fully tested.Kevin Lim
2006-10-02Updates to fix merge issues and bring almost everything up to working speed. ...Kevin Lim
2006-09-30Merge ktlim@zamp:./local/clean/o3-merge/m5Kevin Lim
2006-08-31add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throug...Korey Sewell
2006-07-23This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...Korey Sewell
2006-06-16Two updates that got combined into one ChangeSet accidentally. They're both ...Kevin Lim
2006-06-14Minor code cleanup of BaseDynInst.Kevin Lim
2006-06-12Clean up/shift some code around.Kevin Lim