| Age | Commit message (Expand) | Author |
|---|
| 2015-09-15 | cpu, o3: consider split requests for LSQ checksnoop operations | Hongil Yoon |
| 2015-08-07 | base: Declare a type for context IDs | Andreas Sandberg |
| 2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
| 2015-07-26 | cpu: implements vector registers | Nilay Vaish |
| 2015-05-15 | misc: Appease gcc 5.1 | Andreas Hansson |
| 2015-05-05 | mem, cpu: Add a separate flag for strictly ordered memory | Andreas Sandberg |
| 2015-03-02 | cpu: o3 register renaming request handling improved | Rekai |
| 2015-02-11 | sim: Move the BaseTLB to src/arch/generic/ | Andreas Sandberg |
| 2015-01-25 | sim: Clean up InstRecord | Ali Saidi |
| 2014-11-06 | x86 isa: This patch attempts an implementation at mwait. | Marc Orr |
| 2014-10-16 | arch: Use shared_ptr for all Faults | Andreas Hansson |
| 2014-09-27 | arch: Use const StaticInstPtr references where possible | Andreas Hansson |
| 2014-09-03 | arch, cpu: Factor out the ExecContext into a proper base class | Andreas Sandberg |
| 2014-05-09 | cpu, arm: Allow the specification of a socket field | Akash Bagdia |
| 2014-03-07 | cpu: Make CPU and ThreadContext getters const | Andreas Hansson |
| 2014-01-24 | cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo... | Ali Saidi |
| 2014-01-24 | mem: per-thread cache occupancy and per-block ages | Dam Sunwoo |
| 2013-10-17 | cpu: Fix O3 uncacheable load that is replayed but misses the TLB | Ali Saidi |
| 2013-10-15 | cpu: add a condition-code register class | Yasuko Eckert |
| 2013-07-18 | mem: Set the cache line size on a system level | Andreas Hansson |
| 2012-06-05 | O3: Clean up the O3 structures and try to pack them a bit better. | Ali Saidi |
| 2012-06-05 | sim: Remove FastAlloc | Ali Saidi |
| 2012-03-19 | gcc: Clean-up of non-C++0x compliant code, first steps | Andreas Hansson |
| 2012-03-09 | CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable | Geoffrey Blake |
| 2012-02-24 | CPU: Round-two unifying instr/data CPU ports across models | Andreas Hansson |
| 2012-02-12 | mem: Add a master ID to each request object. | Ali Saidi |
| 2012-02-07 | Faults: Turn off arch/faults.hh | Gabe Black |
| 2012-01-31 | Merge with head, hopefully the last time for this batch. | Gabe Black |
| 2012-01-31 | CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 | Geoffrey Blake |
| 2011-11-18 | SE/FS: Get rid of includes of config/full_system.hh. | Gabe Black |
| 2011-09-13 | LSQ: Only trigger a memory violation with a load/load if the value changes. | Ali Saidi |
| 2011-09-09 | StaticInst: Merge StaticInst and StaticInstBase. | Gabe Black |
| 2011-08-14 | O3: Add a pointer to the macroop for a microop in the dyninst. | Gabe Black |
| 2011-08-07 | Translation: Use a pointer type as the template argument. | Gabe Black |
| 2011-08-02 | O3: Get rid of the raw ExtMachInst constructor on DynInsts. | Gabe Black |
| 2011-07-02 | ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. | Gabe Black |
| 2011-07-02 | ExecContext: Get rid of the now unused read/write templated functions. | Gabe Black |
| 2011-04-04 | CPU: Remove references to memory copy operations | Ali Saidi |
| 2011-04-04 | O3: Tighten memory order violation checking to 16 bytes. | Ali Saidi |
| 2011-02-11 | O3: Enhance data address translation by supporting hardware page table walkers. | Giacomo Gabrielli |
| 2010-12-07 | O3: Support squashing all state after special instruction | Ali Saidi |
| 2010-12-07 | O3: Make all instructions that write a misc. register not perform the write u... | Giacomo Gabrielli |
| 2010-11-08 | ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. | Ali Saidi |
| 2010-10-31 | ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. | Gabe Black |
| 2010-09-13 | Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. | Gabe Black |
| 2010-08-23 | CPU: Make Exec trace to print predication result (if false) for memory instru... | Min Kyu Jeong |
| 2010-08-23 | ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate. | Min Kyu Jeong |
| 2010-08-23 | CPU: Set a default value when readBytes faults. | Ali Saidi |
| 2010-08-13 | CPU: Add readBytes and writeBytes functions to the exec contexts. | Gabe Black |
| 2010-02-20 | BaseDynInst: Preserve the faults returned from read and write. | Timothy M. Jones |
