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path: root/src/cpu/base_dyn_inst_impl.hh
AgeCommit message (Expand)Author
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
2010-11-08ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-08-23ARM: mark msr/mrs instructions as SerializeBefore/AfterMin Kyu Jeong
2010-08-23ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.Min Kyu Jeong
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2008-11-10O3CPU: Make the instcount debugging stuff per-cpu.Clint Smullen
2008-03-06O3CPU: Don't call dumpInsts if DEBUG is not definedVilas Sridharan
2007-06-20Fix compiler errors.Gabe Black
2007-04-14Add support for microcode and pull out the special branch delay slot handling...Gabe Black
2007-03-23Two fixes:Kevin Lim
2006-12-16Accidently "cleaned" away the NPC parameter to the constructor.Gabe Black
2006-12-16Added a predicted NPC field, explicitly stored whether the instruction was pr...Gabe Black
2006-10-23Add in support for LL/SC in the O3 CPU. Needs to be fully tested.Kevin Lim
2006-10-08Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().Steve Reinhardt
2006-08-15Cleaned up include files and got rid of many using directives in header files.Gabe Black
2006-07-23This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...Korey Sewell
2006-06-17Split off instantiation into separate CC files for each of the models. This ...Kevin Lim