| Age | Commit message (Expand) | Author |
|---|
| 2015-09-15 | cpu, o3: consider split requests for LSQ checksnoop operations | Hongil Yoon |
| 2014-09-27 | arch: Use const StaticInstPtr references where possible | Andreas Hansson |
| 2014-01-24 | cpu: Add support for instructions that zero cache lines. | Ali Saidi |
| 2013-10-17 | cpu: add consistent guarding to *_impl.hh files. | Matt Horsnell |
| 2012-06-05 | O3: Clean up the O3 structures and try to pack them a bit better. | Ali Saidi |
| 2012-03-09 | CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable | Geoffrey Blake |
| 2012-03-02 | DynInst: get rid of dead MyHash code. | Steve Reinhardt |
| 2012-01-31 | CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 | Geoffrey Blake |
| 2011-09-13 | LSQ: Only trigger a memory violation with a load/load if the value changes. | Ali Saidi |
| 2011-08-14 | O3: Add a pointer to the macroop for a microop in the dyninst. | Gabe Black |
| 2011-08-02 | O3: Get rid of the raw ExtMachInst constructor on DynInsts. | Gabe Black |
| 2011-04-15 | trace: reimplement the DTRACE function so it doesn't use a vector | Nathan Binkert |
| 2011-04-15 | includes: sort all includes | Nathan Binkert |
| 2011-02-11 | O3: Enhance data address translation by supporting hardware page table walkers. | Giacomo Gabrielli |
| 2010-11-08 | ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. | Ali Saidi |
| 2010-10-31 | ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. | Gabe Black |
| 2010-08-23 | ARM: mark msr/mrs instructions as SerializeBefore/After | Min Kyu Jeong |
| 2010-08-23 | ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate. | Min Kyu Jeong |
| 2009-09-23 | arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh | Nathan Binkert |
| 2008-11-10 | O3CPU: Make the instcount debugging stuff per-cpu. | Clint Smullen |
| 2008-03-06 | O3CPU: Don't call dumpInsts if DEBUG is not defined | Vilas Sridharan |
| 2007-06-20 | Fix compiler errors. | Gabe Black |
| 2007-04-14 | Add support for microcode and pull out the special branch delay slot handling... | Gabe Black |
| 2007-03-23 | Two fixes: | Kevin Lim |
| 2006-12-16 | Accidently "cleaned" away the NPC parameter to the constructor. | Gabe Black |
| 2006-12-16 | Added a predicted NPC field, explicitly stored whether the instruction was pr... | Gabe Black |
| 2006-10-23 | Add in support for LL/SC in the O3 CPU. Needs to be fully tested. | Kevin Lim |
| 2006-10-08 | Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable(). | Steve Reinhardt |
| 2006-08-15 | Cleaned up include files and got rid of many using directives in header files. | Gabe Black |
| 2006-07-23 | This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,... | Korey Sewell |
| 2006-06-17 | Split off instantiation into separate CC files for each of the models. This ... | Kevin Lim |
