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path: root/src/cpu/checker/cpu.hh
AgeCommit message (Expand)Author
2015-09-30cpu,isa,mem: Add per-thread wakeup logicMitch Hayenga
2015-09-30cpu: Add per-thread monitorsMitch Hayenga
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-09-19arch: Pass faults by const reference where possibleAndreas Hansson
2014-09-03arch, cpu: Factor out the ExecContext into a proper base classAndreas Sandberg
2014-01-24checker: CheckerCPU handling of MiscRegs was incorrectGeoffrey Blake
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-10-15cpu: rename *_DepTag constants to *_Reg_BaseSteve Reinhardt
2013-03-26cpu: Remove CpuPort and use MasterPort in the CPU classesAndreas Hansson
2012-08-28Checker: Fix checker CPU portsAndreas Hansson
2012-05-26CPU: Merge the predecoder and decoder.Gabe Black
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-09CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPUGeoffrey Blake
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2011-11-18SE/FS: Get rid of includes of config/full_system.hh.Gabe Black
2011-11-18SE/FS: Get rid of FULL_SYSTEM in the CPU directory.Gabe Black
2011-04-15includes: sort all includesNathan Binkert
2010-11-08ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-08-31CPU: Get rid of the unused ev5_trap function on the simple and checker CPUs.Gabe Black
2010-06-03Minor remote GDB cleanup.Steve Reinhardt
2009-07-08Registers: Get rid of the float register width parameter.Gabe Black
2009-04-08tlb: Don't separate the TLB classes into an instruction TLB and a data TLBGabe Black
2009-02-25CPU: Get rid of translate... functions from various interface classes.Gabe Black
2008-10-20O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo...Ali Saidi
2008-10-11CPU: Eliminate the simPalCheck funciton.Gabe Black
2008-10-11CPU: Eliminate the hwrei function.Gabe Black
2008-09-10style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul...Ali Saidi
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
2008-02-26TLB: Make a TLB base class and put a virtual demapPage function in it.Gabe Black
2007-03-07*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscRegAli Saidi
2006-12-12Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(In...Steve Reinhardt
2006-11-03Got rid of "inPalMode". Some places are still effectively checking if they ar...Gabe Black
2006-11-01Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
2006-11-01Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register ...Gabe Black
2006-10-31Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...Kevin Lim
2006-10-31Move IntrFlag into the MiscRegFile and get rid of specialized accessor functi...Gabe Black
2006-10-02Updates to fix merge issues and bring almost everything up to working speed. ...Kevin Lim
2006-09-30Merge ktlim@zamp:./local/clean/o3-merge/m5Kevin Lim
2006-07-19Minor changes to reflect state used for regression stats.Kevin Lim
2006-07-07Support Ron's changes for hooking up ports.Kevin Lim
2006-07-05Remove sampler and serializer. Now they are handled through C++ interacting ...Kevin Lim
2006-06-16Checker updates.Kevin Lim
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