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path: root/src/cpu/checker
AgeCommit message (Expand)Author
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
2015-02-11sim: Move the BaseTLB to src/arch/generic/Andreas Sandberg
2015-01-25cpu: Remove all notion that we know when the cpu is misspeculating.Ali Saidi
2015-01-22mem: Clean up Request initialisationAndreas Hansson
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-10-29cpu: Add support to checker for CACHE_BLOCK_ZERO commands.Ali Saidi
2014-10-09cpu: Remove Ozone CPU from the source treeMitch Hayenga
2014-09-27arch: Use const StaticInstPtr references where possibleAndreas Hansson
2014-09-27scons: Address issues related to gcc 4.9.1Andreas Hansson
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-09-19arch: Pass faults by const reference where possibleAndreas Hansson
2014-09-12style: Fix line continuation, especially in debug messagesAndrew Bardsley
2014-05-13mem: Refactor assignment of Packet typesCurtis Dunham
2014-09-03arch, cpu: Factor out the ExecContext into a proper base classAndreas Sandberg
2014-05-09cpu, arm: Allow the specification of a socket fieldAkash Bagdia
2014-03-07cpu: Make CPU and ThreadContext getters constAndreas Hansson
2014-01-24checker: CheckerCPU handling of MiscRegs was incorrectGeoffrey Blake
2014-01-24arch, cpu: Add support for flattening misc register indexes.Ali Saidi
2013-11-15cpu: Fix Checker register index useAndreas Hansson
2013-10-17cpu: add consistent guarding to *_impl.hh files.Matt Horsnell
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-10-15cpu: rename *_DepTag constants to *_Reg_BaseSteve Reinhardt
2013-10-15cpu: clean up architectural register classificationSteve Reinhardt
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-03-26cpu: Remove CpuPort and use MasterPort in the CPU classesAndreas Hansson
2013-01-07cpu: Implement a flat register interface in thread contextsAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2013-01-07cpu: rename the misleading inSyscall to noSquashFromTCAli Saidi
2013-01-04Decoder: Remove the thread context get/set from the decoder.Gabe Black
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Checker: Fix checker CPU portsAndreas Hansson
2012-05-26CPU: Merge the predecoder and decoder.Gabe Black
2012-05-25Decode: Make the Decoder class defined per ISA.Gabe Black
2012-05-10gem5: fix a number of use after free issuesAli Saidi
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-09CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPUGeoffrey Blake
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
2012-02-24MEM: Make port proxies use references rather than pointersAndreas Hansson
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-07Checker: Access workload element 0 only if there is an element 0.Gabe Black
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-28Merge with the main repo.Gabe Black
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson