| Age | Commit message (Expand) | Author |
|---|
| 2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter |
| 2016-08-15 | cpu, arch: fix the type used for the request flags | Nikos Nikoleris |
| 2016-04-07 | mem: Remove threadId from memory request class | Mitch Hayenga |
| 2016-04-06 | Revert power patch sets with unexpected interactions | Andreas Sandberg |
| 2016-04-05 | mem: Remove threadId from memory request class | Mitch Hayenga |
| 2016-02-23 | scons: Add missing override to appease clang | Andreas Hansson |
| 2015-10-12 | misc: Add explicit overrides and fix other clang >= 3.5 issues | Andreas Hansson |
| 2015-10-12 | misc: Remove redundant compiler-specific defines | Andreas Hansson |
| 2015-09-30 | cpu,isa,mem: Add per-thread wakeup logic | Mitch Hayenga |
| 2015-09-30 | cpu: Add per-thread monitors | Mitch Hayenga |
| 2015-08-07 | base: Declare a type for context IDs | Andreas Sandberg |
| 2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
| 2015-07-26 | cpu: implements vector registers | Nilay Vaish |
| 2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
| 2015-02-16 | arch: Make readMiscRegNoEffect const throughout | Andreas Hansson |
| 2015-02-11 | sim: Move the BaseTLB to src/arch/generic/ | Andreas Sandberg |
| 2015-01-25 | cpu: Remove all notion that we know when the cpu is misspeculating. | Ali Saidi |
| 2015-01-22 | mem: Clean up Request initialisation | Andreas Hansson |
| 2014-11-06 | x86 isa: This patch attempts an implementation at mwait. | Marc Orr |
| 2014-10-29 | cpu: Add support to checker for CACHE_BLOCK_ZERO commands. | Ali Saidi |
| 2014-10-09 | cpu: Remove Ozone CPU from the source tree | Mitch Hayenga |
| 2014-09-27 | arch: Use const StaticInstPtr references where possible | Andreas Hansson |
| 2014-09-27 | scons: Address issues related to gcc 4.9.1 | Andreas Hansson |
| 2014-09-20 | alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate | Mitch Hayenga |
| 2014-09-19 | arch: Pass faults by const reference where possible | Andreas Hansson |
| 2014-09-12 | style: Fix line continuation, especially in debug messages | Andrew Bardsley |
| 2014-05-13 | mem: Refactor assignment of Packet types | Curtis Dunham |
| 2014-09-03 | arch, cpu: Factor out the ExecContext into a proper base class | Andreas Sandberg |
| 2014-05-09 | cpu, arm: Allow the specification of a socket field | Akash Bagdia |
| 2014-03-07 | cpu: Make CPU and ThreadContext getters const | Andreas Hansson |
| 2014-01-24 | checker: CheckerCPU handling of MiscRegs was incorrect | Geoffrey Blake |
| 2014-01-24 | arch, cpu: Add support for flattening misc register indexes. | Ali Saidi |
| 2013-11-15 | cpu: Fix Checker register index use | Andreas Hansson |
| 2013-10-17 | cpu: add consistent guarding to *_impl.hh files. | Matt Horsnell |
| 2013-10-15 | cpu: add a condition-code register class | Yasuko Eckert |
| 2013-10-15 | cpu: rename *_DepTag constants to *_Reg_Base | Steve Reinhardt |
| 2013-10-15 | cpu: clean up architectural register classification | Steve Reinhardt |
| 2013-07-18 | mem: Set the cache line size on a system level | Andreas Hansson |
| 2013-03-26 | cpu: Remove CpuPort and use MasterPort in the CPU classes | Andreas Hansson |
| 2013-01-07 | cpu: Implement a flat register interface in thread contexts | Andreas Sandberg |
| 2013-01-07 | arch: Make the ISA class inherit from SimObject | Andreas Sandberg |
| 2013-01-07 | cpu: rename the misleading inSyscall to noSquashFromTC | Ali Saidi |
| 2013-01-04 | Decoder: Remove the thread context get/set from the decoder. | Gabe Black |
| 2012-08-28 | Clock: Add a Cycles wrapper class and use where applicable | Andreas Hansson |
| 2012-08-28 | Checker: Fix checker CPU ports | Andreas Hansson |
| 2012-05-26 | CPU: Merge the predecoder and decoder. | Gabe Black |
| 2012-05-25 | Decode: Make the Decoder class defined per ISA. | Gabe Black |
| 2012-05-10 | gem5: fix a number of use after free issues | Ali Saidi |
| 2012-04-14 | MEM: Remove the Broadcast destination from the packet | Andreas Hansson |
| 2012-04-06 | MEM: Enable multiple distributed generalized memories | Andreas Hansson |
