Age | Commit message (Expand) | Author |
2019-09-23 | cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor> | Jordi Vaquero |
2019-08-28 | cpu: Make get(Data|Inst)Port return a Port and not a MasterPort. | Gabe Black |
2019-05-30 | arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy. | Gabe Black |
2019-05-30 | cpu, sim: Return PortProxy &s from all the proxy accessors. | Gabe Black |
2019-05-11 | cpu,mem: Add support for partial loads/stores and wide mem. accesses | Giacomo Gabrielli |
2019-05-11 | cpu: Add a memory access predicate | Giacomo Gabrielli |
2019-04-30 | cpu: alpha: Delete all occurrances of the simPalCheck function. | Gabe Black |
2019-04-30 | cpu: Remove hwrei from the generic interfaces. | Gabe Black |
2019-04-30 | arch: cpu: Track kernel stats using the base ISA agnostic type. | Gabe Black |
2019-04-29 | cpu: Get rid of the (read|set)RegOtherThread methods. | Gabe Black |
2019-04-22 | cpu: Eliminate the ProxyThreadContext class. | Gabe Black |
2019-02-19 | cpu: Add ISA* getter in Thread interface | Giacomo Gabrielli |
2019-02-08 | cpu: support atomic memory request type with AtomicOpFunctor | Tuan Ta |
2019-02-05 | misc: added missing override specifier | Andrea Mondelli |
2019-02-01 | cpu, arch: Replace the CCReg type with RegVal. | Gabe Black |
2019-01-31 | arch: cpu: Rename *FloatRegBits* to *FloatReg*. | Gabe Black |
2019-01-30 | arch,cpu: Add vector predicate registers | Giacomo Gabrielli |
2019-01-22 | arch: cpu: Stop passing around misc registers by reference. | Gabe Black |
2019-01-16 | cpu: dev: sim: gpu-compute: Banish some ISA specific register types. | Gabe Black |
2018-12-20 | arch, cpu: Remove float type accessors. | Gabe Black |
2018-11-28 | cpu,arch-arm: Initialise data members | Rekai Gonzalez-Alberquilla |
2018-11-16 | cpu: Fix the usage of const DynInstPtr | Rekai Gonzalez-Alberquilla |
2018-06-11 | misc: Using smart pointers for memory Requests | Giacomo Travaglini |
2018-06-11 | misc: Substitute pointer to Request with aliased RequestPtr | Giacomo Travaglini |
2018-04-27 | sim,cpu,mem,arch: Introduced MasterInfo data structure | Giacomo Travaglini |
2018-01-09 | cpu, power: Get rid of the remnants of the EA computation insts. | Gabe Black |
2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
2017-12-05 | cpu: Add support for CMOs in the cpu models | Nikos Nikoleris |
2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
2017-07-05 | cpu: Result refactoring | Rekai Gonzalez-Alberquilla |
2017-07-05 | cpu: Simplify the rename interface and use RegId | Rekai Gonzalez-Alberquilla |
2017-07-05 | arch, cpu: Architectural Register structural indexing | Nathanael Premillieu |
2017-02-27 | syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess s... | Brandon Potter |
2015-07-20 | syscall_emul: [patch 13/22] add system call retry capability | Brandon Potter |
2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter |
2016-08-15 | cpu, arch: fix the type used for the request flags | Nikos Nikoleris |
2016-04-07 | mem: Remove threadId from memory request class | Mitch Hayenga |
2016-04-06 | Revert power patch sets with unexpected interactions | Andreas Sandberg |
2016-04-05 | mem: Remove threadId from memory request class | Mitch Hayenga |
2016-02-23 | scons: Add missing override to appease clang | Andreas Hansson |
2015-10-12 | misc: Add explicit overrides and fix other clang >= 3.5 issues | Andreas Hansson |
2015-10-12 | misc: Remove redundant compiler-specific defines | Andreas Hansson |
2015-09-30 | cpu,isa,mem: Add per-thread wakeup logic | Mitch Hayenga |
2015-09-30 | cpu: Add per-thread monitors | Mitch Hayenga |
2015-08-07 | base: Declare a type for context IDs | Andreas Sandberg |
2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
2015-07-26 | cpu: implements vector registers | Nilay Vaish |
2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
2015-02-16 | arch: Make readMiscRegNoEffect const throughout | Andreas Hansson |
2015-02-11 | sim: Move the BaseTLB to src/arch/generic/ | Andreas Sandberg |