gem5 - gem5

Age	Commit message (Expand)	Author
2013-02-15	cpu: Add CPU metadata om the Python classes	Andreas Sandberg
2013-01-24	branch predictor: move out of o3 and inorder cpus	Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-09-07	Param: Transition to Cycles for relevant parameters	Andreas Hansson
2012-08-21	CPU: Remove overloaded function_trace_start parameter	Andreas Hansson
2012-02-24	CPU: Round-two unifying instr/data CPU ports across models	Andreas Hansson
2012-01-17	CPU: Moving towards a more general port across CPU models	Andreas Hansson
2011-02-04	inorder: add a fetch buffer to fetch unit	Korey Sewell
2011-02-04	inorder: stage width as a python parameter	Korey Sewell
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
2010-01-31	configs/inorder: add options for switch-on-miss to inorder cpu	Korey Sewell
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
2009-03-04	InOrder didnt have all it's params set to a default value, which is now requ...	Korey Sewell
2009-02-10	InOrder: Import new inorder CPU model from MIPS.	Korey Sewell