gem5 - gem5

Age	Commit message (Collapse)	Author
2015-04-20	cpu: Remove the InOrderCPU from the tree	Andreas Hansson
	This patch takes the final step in removing the InOrderCPU from the tree. Rest in peace. The MinorCPU is now used to model an in-order microarchitecture, and long term the MinorCPU will eventually be renamed InOrderCPU.
2013-01-24	branch predictor: move out of o3 and inorder cpus	Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
	This patch moves the branch predictor files in the o3 and inorder directories to src/cpu/pred. This allows sharing the branch predictor across different cpu models. This patch was originally posted by Timothy Jones in July 2010 but never made it to the repository. --HG-- rename : src/cpu/o3/bpred_unit.cc => src/cpu/pred/bpred_unit.cc rename : src/cpu/o3/bpred_unit.hh => src/cpu/pred/bpred_unit.hh rename : src/cpu/o3/bpred_unit_impl.hh => src/cpu/pred/bpred_unit_impl.hh rename : src/cpu/o3/sat_counter.hh => src/cpu/pred/sat_counter.hh
2011-06-19	inorder: stall stores on store conditionals & compare/swaps	Korey Sewell

2011-06-02	scons: rename TraceFlags to DebugFlags	Nathan Binkert

2011-02-12	inorder: clean up the old way of inst. scheduling	Korey Sewell
	remove remnants of old way of instruction scheduling which dynamically allocated a new resource schedule for every instruction
2011-02-12	inorder: utilize cached skeds in pipeline	Korey Sewell
	allow the pipeline and resources to use the cached instruction schedule and resource sked iterator
2011-02-04	inorder: implement separate fetch unit	Korey Sewell
	instead of having one cache-unit class be responsible for both data and code accesses, separate code that is just for fetch in it's own derived class off the original base class. This makes the code easier to manage as well as handle future cases of special fetch handling
2010-12-20	Style: Replace some tabs with spaces.	Gabe Black

2010-06-25	inorder: resource scheduling backend	Korey Sewell
	replace priority queue with vector of lists(1 list per stage) and place inside a class so that we have more control of when an instruction uses a particular schedule entry ... also, this is the 1st step toward making the InOrderCPU fully parameterizable. See the wiki for details on this process
2010-03-22	inorder: fix address list bug	Korey Sewell

2010-01-31	inorder: inst count mgmt	Korey Sewell

2010-01-31	inorder: add threadmodel flag	Korey Sewell
	this prints out messages relative to what threading model is being used (smt, switch-on-miss, single, etc.)
2009-09-15	inorder-alpha-fs: edit inorder model to compile FS mode	Korey Sewell

2009-05-12	inorder-tlb-cunit: merge the TLB as implicit to any memory access	Korey Sewell
	TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory and the result is checked before it's sent out to memory. * * *
2009-05-12	inorder-o3: allow both to compile together	Korey Sewell
	allow InOrder and O3CPU to be compiled at the same time: need to make branch prediction filed shared by both models
2009-03-04	Give each resource in InOrder it's own TraceFlag instead of just standard ↵	Korey Sewell
	'Resource' flag
2009-03-04	Remove unused functions/comments cluttering up the code.	Korey Sewell

2009-02-20	Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up ↵	Korey Sewell
	comments and O3 extensions InOrder Thread Context
2009-02-10	InOrder: Import new inorder CPU model from MIPS.	Korey Sewell
	This model currently only works in MIPS_SE mode, so it will take some effort to clean it up and make it generally useful. Hopefully people are willing to help make that happen!