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invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
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path:
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src
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cpu
/
inorder
/
cpu.cc
Age
Commit message (
Expand
)
Author
2013-10-15
cpu: add a condition-code register class
Yasuko Eckert
2013-10-15
cpu/inorder: merge register class enums
Steve Reinhardt
2013-10-15
cpu: clean up architectural register classification
Steve Reinhardt
2013-04-22
sim: separate nextCycle() and clockEdge() in clockedObjects
Dam Sunwoo
2013-03-26
cpu: Remove CpuPort and use MasterPort in the CPU classes
Andreas Hansson
2013-02-15
sim: Add a system-global option to bypass caches
Andreas Sandberg
2013-02-15
cpu: Refactor memory system checks
Andreas Sandberg
2013-01-07
cpu: Rename defer_registration->switched_out
Andreas Sandberg
2013-01-07
cpu: Check that the memory system is in the correct mode
Andreas Sandberg
2013-01-07
arch: Make the ISA class inherit from SimObject
Andreas Sandberg
2013-01-07
cpu: rename the misleading inSyscall to noSquashFromTC
Ali Saidi
2012-08-28
Clock: Add a Cycles wrapper class and use where applicable
Andreas Hansson
2012-08-28
Clock: Rework clocks to avoid tick-to-cycle transformations
Andreas Hansson
2012-08-06
process: add progName() virtual function
Steve Reinhardt
2012-07-09
Port: Align port names in C++ and Python
Andreas Hansson
2012-06-05
cpu: Don't init simple and inorder CPUs if they are defered.
Anthony Gutierrez
2012-05-26
CPU: Merge the predecoder and decoder.
Gabe Black
2012-05-25
Decode: Make the Decoder class defined per ISA.
Gabe Black
2012-05-01
MEM: Separate requests and responses for timing accesses
Andreas Hansson
2012-04-14
MEM: Separate snoops and normal memory requests/responses
Andreas Hansson
2012-03-30
CPU: Unify initMemProxies across CPUs and simulation modes
Andreas Hansson
2012-03-02
CPU: Check that the interrupt controller is created when needed
Andreas Hansson
2012-02-24
CPU: Round-two unifying instr/data CPU ports across models
Andreas Hansson
2012-02-12
cpu: add separate stats for insts/ops both globally and per cpu model
Anthony Gutierrez
2012-01-31
Merge with head, hopefully the last time for this batch.
Gabe Black
2012-01-31
clang: Enable compiling gem5 using clang 2.9 and 3.0
Koan-Sin Tan
2012-01-28
Merge with the main repo.
Gabe Black
2012-01-17
MEM: Add port proxies instead of non-structural ports
Andreas Hansson
2012-01-07
Merge with main repository.
Gabe Black
2011-11-18
SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
Gabe Black
2011-11-01
SE/FS: Expose the same methods on the CPUs in SE and FS modes.
Gabe Black
2011-10-31
SE/FS: Make the functions available from the TC consistent between SE and FS.
Gabe Black
2011-10-31
GCC: Get everything working with gcc 4.6.1.
Gabe Black
2011-10-30
SE/FS: Build the base process class in FS.
Gabe Black
2011-09-09
Decode: Pull instruction decoding out of the StaticInst class into its own.
Gabe Black
2011-06-19
inorder: se: squash after syscalls
Korey Sewell
2011-06-19
inorder: cleanup dprintfs in cache unit
Korey Sewell
2011-06-19
inorder: se compile fixes
Korey Sewell
2011-06-19
inorder: add necessary debug flag header files
Korey Sewell
2011-06-19
inorder: use trapPending flag to manage traps
Korey Sewell
2011-06-19
inorder: dont handle multiple faults on same cycle
Korey Sewell
2011-06-19
inorder: check for interrupts each tick
Korey Sewell
2011-06-19
inorder: explicit fault check
Korey Sewell
2011-06-19
inorder: squash and trap behind a tlb fault
Korey Sewell
2011-06-19
inorder: make InOrder CPU FS compilable/visible
Korey Sewell
2011-06-19
inorder: redefine DynInst FP result type
Korey Sewell
2011-06-19
inorder: treat SE mode syscalls as a trapping instruction
Korey Sewell
2011-06-19
inorder: cleanup events in resource pool
Korey Sewell
2011-06-19
inorder: branch predictor update
Korey Sewell
2011-06-19
inorder: no dep. tracking for zero reg
Korey Sewell
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