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Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.
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replace priority queue with vector of lists(1 list per stage) and place inside a class
so that we have more control of when an instruction uses a particular schedule entry
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also, this is the 1st step toward making the InOrderCPU fully parameterizable. See the
wiki for details on this process
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also, remove inst-req stats as default.good for debugging
but in terms of pure processor stats they aren't useful
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use nextCycle to calculate ticks after addition
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Make sure that instructions are dereferenced/deleted twice by marking they are
on the remove list
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- m5 line enforcement on use_def.cc,hh
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add idle/run/utilization stats for each pipeline stage
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set Active/Suspended/Halted status for threads. useful for system when determining
if/when to exit simulation
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Halt is called from the exit() system call while
deallocate is unused. So to clear up things, just
use halt and remove deallocate.
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when threads are switching in/out the CPU, we need to keep
track of special cases like branches. Add appropriate
variables in ThreadState t track this and then use
these variables when updating pc after context switch
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allow a thread to wakeup and be activated after
it has been in suspended state and another
thread is switched out. Need to give
pipeline stages a "activateThread" function
so that can get to their suspended instruction
when the time is right.
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update/add in the use of isThreadReady & isThreadSuspended
functions.Check in activateThread what list a thread is
on so it can be managed accordingly.
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-Support ability to activate next ready thread after a cache miss
through the activateNextReadyContext/Thread() functions
-To support this a "readyList" of thread ids is added
-After a cache miss, thread will suspend and then call
activitynextreadythread
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allow for events to schedule themselves later if desired. this is important
because of cases like where you need to activate a thread only after the previous
thread has been deactivated. The ordering there has to be enforced
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add code to recognize memory stalls in resources and the pipeline as well
as squash a thread if there is a stall and we are in the switch on cache miss
model
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some events are going to need instruction data when they process, so just
include the instruction in the event construction
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- cpuEventNum
- resReqCount
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This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
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TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst
since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory
and the result is checked before it's sent out to memory.
* * *
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TLB had a bug where if it was stalled and waiting , it would not squash all instructions older than squashed instruction correctly
* * *
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Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions
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Remove namespace from header file. Causes compiler issues that are hard to find
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Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time
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Expose memory access size and flags through instruction object
(temporarily memAccSize and memFlags to get TLB stuff working.)
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For some reason o3 FS init() only called initCPU if the thread state
was Suspended, which was no longer the case. There's no apparent
reason to check, so I whacked the test completely rather than
changing the check to Halted.
The inorder init() was also updated to be symmetric, though the
previous code was just a fancy no-op.
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This provides a common initial status for all threads independent
of CPU model (unlike the prior situation where CPUs initialized
threads to inconsistent states).
This mostly matters for SE mode; in FS mode, ISA-specific startupCPU()
methods generally handle boot-time initialization of thread contexts
(since the right thing to do is ISA-dependent).
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a way for the compiler to play *nice*)
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(1)number from 0-n, not 1-n+1, (2) always check nextStageValid before a stageNum+1 and prevStageValid for a stageNum-1 reference (3) add skidSize() to get StageQueue size for all threads
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generic stages so w/o an ID there is no way to differentiate buffers when debugging
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