| Age | Commit message (Expand) | Author |
|---|
| 2014-03-01 | cpu: Enable fast-forwarding for MIPS InOrderCPU and O3CPU | Christopher Torng |
| 2013-10-15 | cpu: add a condition-code register class | Yasuko Eckert |
| 2013-10-15 | cpu/inorder: merge register class enums | Steve Reinhardt |
| 2013-10-15 | cpu: clean up architectural register classification | Steve Reinhardt |
| 2013-03-26 | cpu: Remove CpuPort and use MasterPort in the CPU classes | Andreas Hansson |
| 2013-02-15 | cpu: Refactor memory system checks | Andreas Sandberg |
| 2013-01-07 | cpu: Rename defer_registration->switched_out | Andreas Sandberg |
| 2013-01-07 | arch: Make the ISA class inherit from SimObject | Andreas Sandberg |
| 2012-08-28 | Clock: Add a Cycles wrapper class and use where applicable | Andreas Hansson |
| 2012-08-28 | Clock: Rework clocks to avoid tick-to-cycle transformations | Andreas Hansson |
| 2012-07-09 | Port: Align port names in C++ and Python | Andreas Hansson |
| 2012-05-26 | CPU: Merge the predecoder and decoder. | Gabe Black |
| 2012-05-25 | Decode: Make the Decoder class defined per ISA. | Gabe Black |
| 2012-05-01 | MEM: Separate requests and responses for timing accesses | Andreas Hansson |
| 2012-04-14 | MEM: Separate snoops and normal memory requests/responses | Andreas Hansson |
| 2012-02-24 | CPU: Round-two unifying instr/data CPU ports across models | Andreas Hansson |
| 2012-02-12 | cpu: add separate stats for insts/ops both globally and per cpu model | Anthony Gutierrez |
| 2012-01-31 | Merge with head, hopefully the last time for this batch. | Gabe Black |
| 2012-01-31 | clang: Enable compiling gem5 using clang 2.9 and 3.0 | Koan-Sin Tan |
| 2012-01-28 | Merge with the main repo. | Gabe Black |
| 2012-01-17 | MEM: Add port proxies instead of non-structural ports | Andreas Hansson |
| 2011-11-18 | SE/FS: Get rid of includes of config/full_system.hh. | Gabe Black |
| 2011-11-18 | SE/FS: Get rid of FULL_SYSTEM in the CPU directory. | Gabe Black |
| 2011-11-01 | SE/FS: Expose the same methods on the CPUs in SE and FS modes. | Gabe Black |
| 2011-10-31 | SE/FS: Make the functions available from the TC consistent between SE and FS. | Gabe Black |
| 2011-09-09 | Decode: Pull instruction decoding out of the StaticInst class into its own. | Gabe Black |
| 2011-06-19 | inorder: use trapPending flag to manage traps | Korey Sewell |
| 2011-06-19 | inorder: dont handle multiple faults on same cycle | Korey Sewell |
| 2011-06-19 | inorder: check for interrupts each tick | Korey Sewell |
| 2011-06-19 | inorder: make InOrder CPU FS compilable/visible | Korey Sewell |
| 2011-06-19 | inorder: redefine DynInst FP result type | Korey Sewell |
| 2011-06-19 | inorder: treat SE mode syscalls as a trapping instruction | Korey Sewell |
| 2011-06-19 | imported patch squash_from_next_stage | Korey Sewell |
| 2011-06-19 | inorder: update event priorities | Korey Sewell |
| 2011-06-19 | inorder: implement trap handling | Korey Sewell |
| 2011-06-19 | inorder: use setupSquash for misspeculation | Korey Sewell |
| 2011-06-19 | inorder: simplify handling of split accesses | Korey Sewell |
| 2011-06-19 | inorder: inst. iterator cleanup | Korey Sewell |
| 2011-06-19 | inorder: add types for dependency checks | Korey Sewell |
| 2011-06-19 | inorder: use flattenIdx for reg indexing | Korey Sewell |
| 2011-06-19 | inorder: use m5_hash_map for skedCache | Korey Sewell |
| 2011-04-15 | includes: sort all includes | Nathan Binkert |
| 2011-03-26 | mips: cleanup ISA-specific code | Korey Sewell |
| 2011-02-18 | inorder: cleanup in destructors | Korey Sewell |
| 2011-02-18 | inorder: remove reqRemoveList | Korey Sewell |
| 2011-02-12 | inorder: stage scheduler for front/back end schedule creation | Korey Sewell |
| 2011-02-12 | inorder: cache instruction schedules | Korey Sewell |
| 2011-02-04 | inorder: stage width as a python parameter | Korey Sewell |
| 2011-01-07 | Replace curTick global variable with accessor functions. | Steve Reinhardt |
| 2011-01-07 | inorder: replace schedEvent() code with reschedule(). | Steve Reinhardt |
