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path: root/src/cpu/inorder/pipeline_stage.cc
AgeCommit message (Expand)Author
2011-06-19inorder: handle serializing instructionsKorey Sewell
2011-06-19inorder: dont handle multiple faults on same cycleKorey Sewell
2011-06-19inorder: check for interrupts each tickKorey Sewell
2011-06-19inorder: don't stall after storesKorey Sewell
2011-06-19inorder: branch predictor updateKorey Sewell
2011-06-19inorder: remove stalls on trap squashKorey Sewell
2011-06-19imported patch squash_from_next_stageKorey Sewell
2011-06-19inorder: implement trap handlingKorey Sewell
2011-04-19stats: rename stats so they can be used as python expressionsNathan Binkert
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-02-18inorder: cleanup in destructorsKorey Sewell
2011-02-18inorder: update pipeline interface for handling finished resource reqsKorey Sewell
2011-02-18inorder: remove request map, use request vectorKorey Sewell
2011-02-18inorder: remove reqRemoveListKorey Sewell
2011-02-12inorder: utilize cached skeds in pipelineKorey Sewell
2011-02-04inorder: fault handlingKorey Sewell
2011-02-04inorder: stage width as a python parameterKorey Sewell
2011-02-04inorder: pipe. stage inst. bufferingKorey Sewell
2011-02-04inorder: change skidBuffer to list instead of queueKorey Sewell
2011-02-04inorder: activity tracking bugKorey Sewell
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-06-24inorder: enforce 78-character ruleKorey Sewell
2010-06-23inorder: stall signal handlingKorey Sewell
2010-01-31inorder: double delete inst bugKorey Sewell
2010-01-31inorder: inst count mgmtKorey Sewell
2010-01-31inorder: add activity statsKorey Sewell
2010-01-31inorder: ctxt switch statsKorey Sewell
2010-01-31inorder: pipeline stage statsKorey Sewell
2010-01-31inorder: enforce stage bandwidthKorey Sewell
2010-01-31inorder: track last branch committedKorey Sewell
2010-01-31inorder: add updatePC event to resPoolKorey Sewell
2010-01-31inorder: ready thread wakeupKorey Sewell
2010-01-31inorder: activate thread on cache missKorey Sewell
2010-01-31inorder: squash on memory stallKorey Sewell
2010-01-31inorder: switch out bufferKorey Sewell
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-05-12inorder-fetch: update model to use predecoderKorey Sewell
2009-05-12inorder-bpred: edits to handle non-delay-slot ISAsKorey Sewell
2009-03-04InOrderCPU: Clean up Constructors to initialize variables correctly (i.e. in ...Korey Sewell
2009-03-04Remove unused functions/comments cluttering up the code.Korey Sewell
2009-03-04make handling of interstage buffers (i.e. StageQueues) more consistent: (1)nu...Korey Sewell
2009-03-04 InOrder didnt have all it's params set to a default value, which is now requ...Korey Sewell
2009-03-04Give TimeBuffer an ID that can be set. Necessary because InOrder uses generic...Korey Sewell
2009-02-10InOrder: Import new inorder CPU model from MIPS.Korey Sewell
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