gem5 - gem5

Age	Commit message (Collapse)	Author
2010-06-25	inorder: resource scheduling backend	Korey Sewell
	replace priority queue with vector of lists(1 list per stage) and place inside a class so that we have more control of when an instruction uses a particular schedule entry ... also, this is the 1st step toward making the InOrderCPU fully parameterizable. See the wiki for details on this process
2010-03-27	inorder: write-hints bug fix	Korey Sewell
	make sure to only read 1 src reg. for write-hint and any other similar 'store' instruction. Reading the source reg when its not necessary can cause the simulator to read from uninitialized values
2010-01-31	inorder: dont allow early loads	Korey Sewell
	- loads were happening on same cycle as the address was generated which is slightly unrealistic. Instead, force address generation to be on separate cycle from load initiation - also, mark the stages in a more traditional way (F-D-X-M-W)
2009-05-12	inorder-tlb-cunit: merge the TLB as implicit to any memory access	Korey Sewell
	TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory and the result is checked before it's sent out to memory. * * *
2009-05-12	inorder-unified-tlb: use unified TLB instead of old TLB model	Korey Sewell

2009-05-12	inorder/alpha-isa: create eaComp object visible to StaticInst through ISA	Korey Sewell
	Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access * * *
2009-02-10	InOrder: Import new inorder CPU model from MIPS.	Korey Sewell
	This model currently only works in MIPS_SE mode, so it will take some effort to clean it up and make it generally useful. Hopefully people are willing to help make that happen!