gem5 - gem5

Age	Commit message (Collapse)	Author
2012-02-24	CPU: Round-two unifying instr/data CPU ports across models	Andreas Hansson
	This patch continues the unification of how the different CPU models create and share their instruction and data ports. Most importantly, it forces every CPU to have an instruction and a data port, and gives these ports explicit getters in the BaseCPU (getDataPort and getInstPort). The patch helps in simplifying the code, make assumptions more explicit, andfurther ease future patches related to the CPU ports. The biggest changes are in the in-order model (that was not modified in the previous unification patch), which now moves the ports from the CacheUnit to the CPU. It also distinguishes the instruction fetch and load-store unit from the rest of the resources, and avoids the use of indices and casting in favour of keeping track of these two units explicitly (since they are always there anyways). The atomic, timing and O3 model simply return references to their already existing ports.
2011-06-19	inorder: implement trap handling	Korey Sewell

2011-04-19	stats: rename stats so they can be used as python expressions	Nathan Binkert

2011-04-15	includes: sort all includes	Nathan Binkert

2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
	This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values.
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert

2009-02-10	InOrder: Import new inorder CPU model from MIPS.	Korey Sewell
	This model currently only works in MIPS_SE mode, so it will take some effort to clean it up and make it generally useful. Hopefully people are willing to help make that happen!