summaryrefslogtreecommitdiff
path: root/src/cpu/inorder/resources/cache_unit.cc
AgeCommit message (Expand)Author
2015-01-25sim: Clean up InstRecordAli Saidi
2014-12-02mem: Add const getters for write packet dataAndreas Hansson
2014-09-19arch: Pass faults by const reference where possibleAndreas Hansson
2014-05-13mem: Refactor assignment of Packet typesCurtis Dunham
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-05-26CPU: Merge the predecoder and decoder.Gabe Black
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-01-28Merge with the main repo.Gabe Black
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2011-11-18SE/FS: Get rid of FULL_SYSTEM in the CPU directory.Gabe Black
2011-06-20InOder: Fix a compile error.Gabe Black
2011-06-19inorder: cleanup dprintfs in cache unitKorey Sewell
2011-06-19inorder: SE mode TLB faultsKorey Sewell
2011-06-19inorder: se compile fixesKorey Sewell
2011-06-19inorder: add necessary debug flag header filesKorey Sewell
2011-06-19inorder/dtb: make sure DTB translate correct addressKorey Sewell
2011-06-19inorder: handle serializing instructionsKorey Sewell
2011-06-19inorder: dont handle multiple faults on same cycleKorey Sewell
2011-06-19inorder: register ports for FS modeKorey Sewell
2011-06-19inorder: check for interrupts each tickKorey Sewell
2011-06-19inorder: squash and trap behind a tlb faultKorey Sewell
2011-06-19inorder: stall stores on store conditionals & compare/swapsKorey Sewell
2011-06-19inorder: remove memdep tracking for default pipelineKorey Sewell
2011-06-19inorder: don't stall after storesKorey Sewell
2011-06-19inorder: don't stall after storesKorey Sewell
2011-06-19inorder: support for compare and swap instsKorey Sewell
2011-06-19inorder: add flatDestReg member to dyninstKorey Sewell
2011-06-19inorder: implement trap handlingKorey Sewell
2011-06-19inorder: DynInst handling of stores for big-endian ISAsKorey Sewell
2011-06-19inorder: simplify handling of split accessesKorey Sewell
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-02-23inorder: cache packet handlingKorey Sewell
2011-02-18inorder: fix cache/fetch unit memory leaksKorey Sewell
2011-02-18inorder: update pipeline interface for handling finished resource reqsKorey Sewell
2011-02-18inorder: remove request map, use request vectorKorey Sewell
2011-02-18inorder: remove reqRemoveListKorey Sewell
2011-02-18inorder: initialize res. req. vectors based on resource bandwidthKorey Sewell
2011-02-12inorder: clean up the old way of inst. schedulingKorey Sewell
2011-02-12inorder: utilize cached skeds in pipelineKorey Sewell
2011-02-04inorder: fault handlingKorey Sewell
2011-02-04inorder: add a fetch buffer to fetch unitKorey Sewell
2011-02-04inorder: overload find-req fnKorey Sewell
2011-02-04inorder: implement separate fetch unitKorey Sewell