gem5 - gem5

Age	Commit message (Collapse)	Author
2011-06-19	inorder: don't stall after stores	Korey Sewell
	once a ST is sent off, it's OK to keep processing, however it's a little more complicated to handle the packet acknowledging the store is completed
2011-06-19	inorder: don't stall after stores	Korey Sewell
	once a ST is sent off, it's OK to keep processing, however it's a little more complicated to handle the packet acknowledging the store is completed
2011-04-15	includes: sort all includes	Nathan Binkert

2011-02-23	inorder: cache packet handling	Korey Sewell
	-use a pointer to CacheReqPacket instead of PacketPtr so correct destructors get called on packet deletion - make sure to delete the packet if the cache blocks the sendTiming request or for some reason we dont use the packet - dont overwrite memory requests since in the worst case an instruction will be replaying a request so no need to keep allocating a new request - we dont use retryPkt so delete it - fetch code was split out already, so just assert that this is a memory reference inst. and that the staticInst is available
2011-02-18	inorder: fix cache/fetch unit memory leaks	Korey Sewell
	--- need to delete the cache request's data on clearRequest() now that we are recycling requests --- fetch unit needs to deallocate the fetch buffer blocks when they are replaced or squashed.
2011-02-18	inorder: remove request map, use request vector	Korey Sewell
	take away all instances of reqMap in the code and make all references use the built-in request vectors inside of each resource. The request map was dynamically allocating a request per instruction. The request vector just allocates N number of requests during instantiation and then the surrounding code is fixed up to reuse those N requests *** setRequest() and clearRequest() are the new accessors needed to define a new request in a resource
2011-02-04	inorder: fault handling	Korey Sewell
	Maintain all information about an instruction's fault in the DynInst object rather than any cpu-request object. Also, if there is a fault during the execution stage then just save the fault inside the instruction and trap once the instruction tries to graduate
2011-02-04	inorder: add a fetch buffer to fetch unit	Korey Sewell
	Give fetch unit it's own parameterizable fetch buffer to read from. Very inefficient (architecturally and in simulation) to continually fetch at the granularity of the wordsize. As expected, the number of fetch memory requests drops dramatically
2011-02-04	inorder: overload find-req fn	Korey Sewell
	no need to have separate function name findSplitRequest, just overload the function
2011-02-04	inorder: implement separate fetch unit	Korey Sewell
	instead of having one cache-unit class be responsible for both data and code accesses, separate code that is just for fetch in it's own derived class off the original base class. This makes the code easier to manage as well as handle future cases of special fetch handling
2010-12-20	Style: Replace some tabs with spaces.	Gabe Black

2010-11-08	ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.	Ali Saidi
	This change modifies the way prefetches work. They are now like normal loads that don't writeback a register. Previously prefetches were supposed to call prefetch() on the exection context, so they executed with execute() methods instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs are blank, meaning that they get executed, but don't actually do anything. On Alpha dead cache copy code was removed and prefetches are now normal ops. They count as executed operations, but still don't do anything and IsMemRef is not longer set on them. On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch instructions. The timing simple CPU doesn't try to do anything special for prefetches now and they execute with the normal memory code path.
2010-08-13	CPU: Add readBytes and writeBytes functions to the exec contexts.	Gabe Black

2010-06-24	inorder: cleanup virtual functions	Korey Sewell
	remove the annotation 'virtual' from function declaration that isnt being derived from
2010-06-24	inorder: enforce 78-character rule	Korey Sewell

2010-01-31	inorder: inst count mgmt	Korey Sewell

2010-01-31	inorder: implement split stores	Korey Sewell

2010-01-31	inorder: implement split loads	Korey Sewell

2010-01-31	inorder: object cleanup in destructors	Korey Sewell

2010-01-31	inorder: recvRetry bug fix	Korey Sewell
	- on certain retry requests you can get an assertion failure - fix by allowing the request to literally "Retry" itself if it wasnt successful before, and then block any requests through cache port while waiting for the cache to be made available for access
2010-01-31	inorder: mem. mgmt. update	Korey Sewell
	update address List and address Map to take into account multiple threads
2010-01-31	inorder: squash on memory stall	Korey Sewell
	add code to recognize memory stalls in resources and the pipeline as well as squash a thread if there is a stall and we are in the switch on cache miss model
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert

2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert

2009-05-12	inorder-tlb-cunit: merge the TLB as implicit to any memory access	Korey Sewell
	TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory and the result is checked before it's sent out to memory. * * *
2009-05-12	inorder-stc: update interface to handle store conditionals	Korey Sewell

2009-05-12	inorder-fetch: update model to use predecoder	Korey Sewell

2009-05-12	inorder-mem: clean up allocation/deletion of requests/packets	Korey Sewell
	* * *
2009-05-12	inorder-mem: skeleton support for prefetch/writehints	Korey Sewell

2009-02-10	Configs: Add support for the InOrder CPU model	Korey Sewell

2009-02-10	InOrder: Import new inorder CPU model from MIPS.	Korey Sewell
	This model currently only works in MIPS_SE mode, so it will take some effort to clean it up and make it generally useful. Hopefully people are willing to help make that happen!