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if a faulting instruction reaches an execution unit,
then ignore it and pass it through the pipeline.
Once we recognize the fault in the graduation unit,
dont allow a second fault to creep in on the same cycle.
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segfault was caused by squashed multiply thats in the process of an event.
use isProcessing flag to handle this and cleanup the MDU code
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At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
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take away all instances of reqMap in the code and make all references use the built-in
request vectors inside of each resource. The request map was dynamically allocating
a request per instruction. The request vector just allocates N number of requests
during instantiation and then the surrounding code is fixed up to reuse those N requests
***
setRequest() and clearRequest() are the new accessors needed to define a new
request in a resource
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allow the pipeline and resources to use the cached instruction schedule and resource
sked iterator
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Maintain all information about an instruction's fault in the DynInst object rather
than any cpu-request object. Also, if there is a fault during the execution stage
then just save the fault inside the instruction and trap once the instruction
tries to graduate
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This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
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Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.
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also, remove inst-req stats as default.good for debugging
but in terms of pure processor stats they aren't useful
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mdu was workign incorrectly for 4+ latency due to incorrectly assuming
multiply was finished the next stage
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Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions
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Remove namespace from header file. Causes compiler issues that are hard to find
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Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time
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Expose memory access size and flags through instruction object
(temporarily memAccSize and memFlags to get TLB stuff working.)
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a way for the compiler to play *nice*)
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required for M5 objects; Also, a # of values need to be reset to 0 (or the appropriate value) before we assume they are OK for use.
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This model currently only works in MIPS_SE mode, so it will take some effort
to clean it up and make it generally useful. Hopefully people are willing to
help make that happen!
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